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[Qemu-devel] [PULL 19/42] target/arm: Move NS TBFLAG from bit 19 to bit
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 19/42] target/arm: Move NS TBFLAG from bit 19 to bit 6 |
Date: |
Mon, 29 Apr 2019 18:00:07 +0100 |
Move the NS TBFLAG down from bit 19 to bit 6, which has not
been used since commit c1e3781090b9d36c60 in 2015, when we
started passing the entire MMU index in the TB flags rather
than just a 'privilege level' bit.
This rearrangement is not strictly necessary, but means that
we can put M-profile-only bits next to each other rather
than scattered across the flag word.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.h | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index eb989d773af..0ea448034b3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3138,6 +3138,12 @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
FIELD(TBFLAG_A32, THUMB, 0, 1)
FIELD(TBFLAG_A32, VECLEN, 1, 3)
FIELD(TBFLAG_A32, VECSTRIDE, 4, 2)
+/*
+ * Indicates whether cp register reads and writes by guest code should access
+ * the secure or nonsecure bank of banked registers; note that this is not
+ * the same thing as the current security state of the processor!
+ */
+FIELD(TBFLAG_A32, NS, 6, 1)
FIELD(TBFLAG_A32, VFPEN, 7, 1)
FIELD(TBFLAG_A32, CONDEXEC, 8, 8)
FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
@@ -3145,11 +3151,6 @@ FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
* checks on the other bits at runtime
*/
FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2)
-/* Indicates whether cp register reads and writes by guest code should access
- * the secure or nonsecure bank of banked registers; note that this is not
- * the same thing as the current security state of the processor!
- */
-FIELD(TBFLAG_A32, NS, 19, 1)
/* For M profile only, Handler (ie not Thread) mode */
FIELD(TBFLAG_A32, HANDLER, 21, 1)
/* For M profile only, whether we should generate stack-limit checks */
--
2.20.1
- [Qemu-devel] [PULL 16/42] target/arm: Clean excReturn bits when tail chaining, (continued)
- [Qemu-devel] [PULL 16/42] target/arm: Clean excReturn bits when tail chaining, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 28/42] target/arm: Implement VLLDM for v7M CPUs with an FPU, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 10/42] target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 41/42] hw/net/lan9118: Export TYPE_LAN9118 and use it instead of hardcoded string, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 12/42] target/arm/helper: don't return early for STKOF faults during stacking, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 27/42] target/arm: Implement VLSTM for v7M CPUs with an FPU, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 34/42] hw/devices: Move TC6393XB declarations into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 20/42] target/arm: Overlap VECSTRIDE and XSCALE_CPAR TB flags, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 11/42] target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 38/42] hw/devices: Move TI touchscreen declarations into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 19/42] target/arm: Move NS TBFLAG from bit 19 to bit 6,
Peter Maydell <=
- [Qemu-devel] [PULL 39/42] hw/devices: Move LAN9118 declarations into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 35/42] hw/devices: Move Blizzard declarations into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 18/42] target/arm: Handle floating point registers in exception return, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 42/42] hw/devices: Move SMSC 91C111 declaration into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 23/42] target/arm: New helper function arm_v7m_mmu_idx_all(), Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 37/42] hw/devices: Move Gamepad declarations into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 26/42] target/arm: Implement M-profile lazy FP state preservation, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 36/42] hw/devices: Move CBus declarations into a new header, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 29/42] target/arm: Enable FPU for Cortex-M4 and Cortex-M33, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 40/42] hw/net/ne2000-isa: Add guards to the header, Peter Maydell, 2019/04/29