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[PATCH 38/45] target/hppa: Implement PSW_X
From: |
Richard Henderson |
Subject: |
[PATCH 38/45] target/hppa: Implement PSW_X |
Date: |
Wed, 24 Apr 2024 17:00:16 -0700 |
Use PAGE_WRITE_INV to temporarily enable write permission
on for a given page, driven by PSW_X being set.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/mem_helper.c | 46 +++++++++++++++++++++++-----------------
1 file changed, 27 insertions(+), 19 deletions(-)
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 84785b5a5c..5eca5e8a1e 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -295,30 +295,38 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr
addr, int mmu_idx,
goto egress;
}
- /* In reverse priority order, check for conditions which raise faults.
- As we go, remove PROT bits that cover the condition we want to check.
- In this way, the resulting PROT will force a re-check of the
- architectural TLB entry for the next access. */
- if (unlikely(!ent->d)) {
- if (type & PAGE_WRITE) {
- /* The D bit is not set -- TLB Dirty Bit Fault. */
- ret = EXCP_TLB_DIRTY;
- }
- prot &= PAGE_READ | PAGE_EXEC;
- }
- if (unlikely(ent->b)) {
- if (type & PAGE_WRITE) {
- /* The B bit is set -- Data Memory Break Fault. */
- ret = EXCP_DMB;
- }
- prot &= PAGE_READ | PAGE_EXEC;
- }
+ /*
+ * In priority order, check for conditions which raise faults.
+ * Remove PROT bits that cover the condition we want to check,
+ * so that the resulting PROT will force a re-check of the
+ * architectural TLB entry for the next access.
+ */
if (unlikely(ent->t)) {
+ prot &= PAGE_EXEC;
if (!(type & PAGE_EXEC)) {
/* The T bit is set -- Page Reference Fault. */
ret = EXCP_PAGE_REF;
}
- prot &= PAGE_EXEC;
+ } else if (!ent->d) {
+ prot &= PAGE_READ | PAGE_EXEC;
+ if (type & PAGE_WRITE) {
+ /* The D bit is not set -- TLB Dirty Bit Fault. */
+ ret = EXCP_TLB_DIRTY;
+ }
+ } else if (unlikely(ent->b)) {
+ prot &= PAGE_READ | PAGE_EXEC;
+ if (type & PAGE_WRITE) {
+ /*
+ * The B bit is set -- Data Memory Break Fault.
+ * Except when PSW_X is set, allow this single access to succeed.
+ * The write bit will be invalidated for subsequent accesses.
+ */
+ if (env->psw_xb & PSW_X) {
+ prot |= PAGE_WRITE_INV;
+ } else {
+ ret = EXCP_DMB;
+ }
+ }
}
egress:
--
2.34.1
- [PATCH 32/45] target/hppa: Store full iaoq_f and page bits of iaoq_d in TB, (continued)
- [PATCH 32/45] target/hppa: Store full iaoq_f and page bits of iaoq_d in TB, Richard Henderson, 2024/04/24
- [PATCH 31/45] linux-user/hppa: Force all code addresses to PRIV_USER, Richard Henderson, 2024/04/24
- [PATCH 26/45] target/hppa: Use TCG_COND_TST* in trans_ftest, Richard Henderson, 2024/04/24
- [PATCH 30/45] target/hppa: Use delay_excp for conditional trap on overflow, Richard Henderson, 2024/04/24
- [PATCH 34/45] target/hppa: Improve hppa_cpu_dump_state, Richard Henderson, 2024/04/24
- [PATCH 36/45] target/hppa: Manage PSW_X and PSW_B in translator, Richard Henderson, 2024/04/24
- [PATCH 21/45] target/hppa: Use TCG_COND_TST* in do_log_cond, Richard Henderson, 2024/04/24
- [PATCH 33/45] target/hppa: Do not mask in copy_iaoq_entry, Richard Henderson, 2024/04/24
- [PATCH 35/45] target/hppa: Split PSW X and B into their own field, Richard Henderson, 2024/04/24
- [PATCH 37/45] target/hppa: Implement PSW_B, Richard Henderson, 2024/04/24
- [PATCH 38/45] target/hppa: Implement PSW_X,
Richard Henderson <=
- [PATCH 39/45] target/hppa: Drop tlb_entry return from hppa_get_physical_address, Richard Henderson, 2024/04/24
- [PATCH 41/45] target/hppa: Implement CF_PCREL, Richard Henderson, 2024/04/24
- [PATCH 44/45] target/hppa: Log cpu state at interrupt, Richard Henderson, 2024/04/24
- [PATCH 43/45] target/hppa: Implement PSW_H, PSW_L, Richard Henderson, 2024/04/24
- [PATCH 42/45] target/hppa: Implement PSW_T, Richard Henderson, 2024/04/24
- [PATCH 45/45] target/hppa: Log cpu state on return-from-interrupt, Richard Henderson, 2024/04/24
- [PATCH 40/45] target/hppa: Adjust priv for B,GATE at runtime, Richard Henderson, 2024/04/24