Re: [Qemu-ppc] Regression in ppc-softmmu when running HelenOS

[Mark Cave-Ayland]

On 14/03/12 02:22, Alexander Graf wrote:

> > 2. Bits 33:36 and 42:47 of SRR1 or HSRR1 are
> > loaded with information specific to the interrupt
> > type.
> >
> > - These bits are not relevant on PPC32 since MSR is only 32-bit.
>
> PowerPC begins counting with the most significant bit, so they are in the 
> 32-bit range.

But I thought that the QEMU order was the reverse as given in the 
specification? For example, on p.735 describing the MSR, the SF (Sixty 
Four) bit flag is described as bit 0, where as in target-ppc/cpu.h 
MSR_SF is given as 63.


ATB,

Mark.