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[Qemu-ppc] [PATCH 1/2] iommu: Replace bus+devfn arguments with PCIDevice
From: |
Knut Omang |
Subject: |
[Qemu-ppc] [PATCH 1/2] iommu: Replace bus+devfn arguments with PCIDevice* in PCIIOMMUFunc |
Date: |
Tue, 21 Oct 2014 00:34:02 +0200 |
The dev pointer is needed by intel_iommu to enable it to store the dma address
pointer
with the device.
Signed-off-by: Knut Omang <address@hidden>
---
hw/alpha/typhoon.c | 2 +-
hw/pci-host/apb.c | 2 +-
hw/pci-host/prep.c | 3 +--
hw/pci-host/q35.c | 5 +++--
hw/pci/pci.c | 7 +++----
hw/ppc/spapr_pci.c | 2 +-
include/hw/pci/pci.h | 4 +++-
7 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index 5310006..62f7178 100644
--- a/hw/alpha/typhoon.c
+++ b/hw/alpha/typhoon.c
@@ -725,7 +725,7 @@ static const MemoryRegionIOMMUOps typhoon_iommu_ops = {
.translate = typhoon_translate_iommu,
};
-static AddressSpace *typhoon_pci_dma_iommu(PCIBus *bus, void *opaque, int
devfn)
+static AddressSpace *typhoon_pci_dma_iommu(PCIDevice *dev, void *opaque)
{
TyphoonState *s = opaque;
return &s->pchip.iommu_as;
diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
index f573875..06b6daa 100644
--- a/hw/pci-host/apb.c
+++ b/hw/pci-host/apb.c
@@ -198,7 +198,7 @@ static inline void pbm_clear_request(APBState *s, unsigned
int irq_num)
s->irq_request = NO_IRQ_REQUEST;
}
-static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
+static AddressSpace *pbm_pci_dma_iommu(PCIDevice *dev, void *opaque)
{
IOMMUState *is = opaque;
diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index 1de3681..ba997a8 100644
--- a/hw/pci-host/prep.c
+++ b/hw/pci-host/prep.c
@@ -194,8 +194,7 @@ static void raven_set_irq(void *opaque, int irq_num, int
level)
qemu_set_irq(pic[irq_num] , level);
}
-static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
- int devfn)
+static AddressSpace *raven_pcihost_set_iommu(PCIDevice *dev, void *opaque)
{
PREPPCIState *s = opaque;
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index b20bad8..c087c96 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -347,11 +347,12 @@ static void mch_reset(DeviceState *qdev)
mch_update(mch);
}
-static AddressSpace *q35_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
+static AddressSpace *q35_host_dma_iommu(PCIDevice *dev, void *opaque)
{
IntelIOMMUState *s = opaque;
VTDAddressSpace **pvtd_as;
- int bus_num = pci_bus_num(bus);
+ int bus_num = pci_bus_num(dev->bus);
+ int devfn = dev->devfn;
assert(0 <= bus_num && bus_num <= VTD_PCI_BUS_MAX);
assert(0 <= devfn && devfn <= VTD_PCI_DEVFN_MAX);
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 6ce75aa..b077173 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -808,7 +808,6 @@ static PCIDevice *do_pci_register_device(PCIDevice
*pci_dev, PCIBus *bus,
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
PCIConfigReadFunc *config_read = pc->config_read;
PCIConfigWriteFunc *config_write = pc->config_write;
- AddressSpace *dma_as;
if (devfn < 0) {
for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
@@ -827,11 +826,11 @@ static PCIDevice *do_pci_register_device(PCIDevice
*pci_dev, PCIBus *bus,
pci_dev->bus = bus;
pci_dev->devfn = devfn;
- dma_as = pci_device_iommu_address_space(pci_dev);
+ pci_dev->dma_as = pci_device_iommu_address_space(pci_dev);
memory_region_init_alias(&pci_dev->bus_master_enable_region,
OBJECT(pci_dev), "bus master",
- dma_as->root, 0,
memory_region_size(dma_as->root));
+ pci_dev->dma_as->root, 0,
memory_region_size(pci_dev->dma_as->root));
memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
address_space_init(&pci_dev->bus_master_as,
&pci_dev->bus_master_enable_region,
name);
@@ -2280,7 +2279,7 @@ AddressSpace *pci_device_iommu_address_space(PCIDevice
*dev)
PCIBus *bus = PCI_BUS(dev->bus);
if (bus->iommu_fn) {
- return bus->iommu_fn(bus, bus->iommu_opaque, dev->devfn);
+ return bus->iommu_fn(dev, bus->iommu_opaque);
}
if (bus->parent_dev) {
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index ad0da7f..656fae3 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -472,7 +472,7 @@ static const MemoryRegionOps spapr_msi_ops = {
/*
* PHB PCI device
*/
-static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
+static AddressSpace *spapr_pci_dma_iommu(PCIDevice *dev, void *opaque)
{
sPAPRPHBState *phb = opaque;
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index c352c7b..4bcf151 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -242,6 +242,7 @@ struct PCIDevice {
char name[64];
PCIIORegion io_regions[PCI_NUM_REGIONS];
AddressSpace bus_master_as;
+ AddressSpace *dma_as;
MemoryRegion bus_master_enable_region;
/* do not access the following fields */
@@ -408,7 +409,8 @@ int pci_parse_devaddr(const char *addr, int *domp, int
*busp,
void pci_device_deassert_intx(PCIDevice *dev);
-typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
+typedef AddressSpace *(*PCIIOMMUFunc)(PCIDevice *, void *);
+void pci_set_dma_address_space(AddressSpace *dma_address_space);
AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
--
1.9.0
[Qemu-ppc] [PATCH 1/2] iommu: Replace bus+devfn arguments with PCIDevice* in PCIIOMMUFunc,
Knut Omang <=
Re: [Qemu-ppc] [PATCH 0/2] intel_iommu: Add support for translation for devices behind bridges, Alexander Graf, 2014/10/20
- Re: [Qemu-ppc] [PATCH 0/2] intel_iommu: Add support for translation for devices behind bridges, Knut Omang, 2014/10/21
- Re: [Qemu-ppc] [PATCH 0/2] intel_iommu: Add support for translation for devices behind bridges, Alexander Graf, 2014/10/21
- Re: [Qemu-ppc] [PATCH 0/2] intel_iommu: Add support for translation for devices behind bridges, Knut Omang, 2014/10/21
- Re: [Qemu-ppc] [PATCH 0/2] intel_iommu: Add support for translation for devices behind bridges, Alexander Graf, 2014/10/21
- Re: [Qemu-ppc] [PATCH 0/2] intel_iommu: Add support for translation for devices behind bridges, Michael S. Tsirkin, 2014/10/21
- Re: [Qemu-ppc] [PATCH 0/2] intel_iommu: Add support for translation for devices behind bridges, Knut Omang, 2014/10/21
- Re: [Qemu-ppc] [PATCH 0/2] intel_iommu: Add support for translation for devices behind bridges, Michael S. Tsirkin, 2014/10/21
Re: [Qemu-ppc] [Qemu-devel] [PATCH 0/2] intel_iommu: Add support for translation for devices behind bridges, Alex Williamson, 2014/10/21
Re: [Qemu-ppc] [Qemu-devel] [PATCH 0/2] intel_iommu: Add support for translation for devices behind bridges, Michael S. Tsirkin, 2014/10/21