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[Qemu-ppc] [PATCH 7/9] target-ppc: Introduce TM Noops
From: |
Tom Musta |
Subject: |
[Qemu-ppc] [PATCH 7/9] target-ppc: Introduce TM Noops |
Date: |
Thu, 18 Dec 2014 10:34:35 -0600 |
Add degenerate implementations of the non-privileged Transactional
Memory instructions tend., tabort*. and tsr. This implementation
simply checks the MSR[TM] bit and then sets CR0 to 0b0000. This
is a reasonable degenerate implementation since transactions are
never allowed to begin and hence MSR[TS] is always 0b00.
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
1 files changed, 38 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index cddfc36..f468a5d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9652,6 +9652,30 @@ static void gen_tbegin(DisasContext *ctx)
gen_helper_tbegin(cpu_env);
}
+#define GEN_TM_NOOP(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ if (unlikely(!ctx->tm_enabled)) { \
+ gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
+ return; \
+ } \
+ /* Because tbegin always fails in QEMU, these user \
+ * space instructions all have a simple implementation: \
+ * \
+ * CR[0] = 0b0 || MSR[TS] || 0b0 \
+ * = 0b0 || 0b00 || 0b0 \
+ */ \
+ tcg_gen_movi_i32(cpu_crf[0], 0); \
+}
+
+GEN_TM_NOOP(tend);
+GEN_TM_NOOP(tabort);
+GEN_TM_NOOP(tabortwc);
+GEN_TM_NOOP(tabortwci);
+GEN_TM_NOOP(tabortdc);
+GEN_TM_NOOP(tabortdci);
+GEN_TM_NOOP(tsr);
+
static opcode_t opcodes[] = {
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
@@ -11067,6 +11091,20 @@ GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
+ PPC_NONE, PPC2_TM),
};
#include "helper_regs.h"
--
1.7.1
- [Qemu-ppc] [PATCH 1/9] target-ppc: Introduce Instruction Type for Transactional Memory, (continued)
- [Qemu-ppc] [PATCH 1/9] target-ppc: Introduce Instruction Type for Transactional Memory, Tom Musta, 2014/12/18
- [Qemu-ppc] [PATCH 3/9] target-ppc: Introduce tm_enabled Bit to CPU State, Tom Musta, 2014/12/18
- [Qemu-ppc] [PATCH 4/9] target-ppc: Power8 Supports Transactional Memory, Tom Musta, 2014/12/18
- [Qemu-ppc] [PATCH 2/9] target-ppc: Introduce Feature Flag for Transactional Memory, Tom Musta, 2014/12/18
- [Qemu-ppc] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields, Tom Musta, 2014/12/18
[Qemu-ppc] [PATCH 6/9] target-ppc: Introduce tbegin, Tom Musta, 2014/12/18
[Qemu-ppc] [PATCH 7/9] target-ppc: Introduce TM Noops,
Tom Musta <=
[Qemu-ppc] [PATCH 8/9] target-ppc: Introduce tcheck, Tom Musta, 2014/12/18
[Qemu-ppc] [PATCH 9/9] target-ppc: Introduce Privileged TM Noops, Tom Musta, 2014/12/18
Re: [Qemu-ppc] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory, Alexander Graf, 2014/12/18