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[Qemu-ppc] [PATCH 3/9] target-ppc: Introduce tm_enabled Bit to CPU State
From: |
Tom Musta |
Subject: |
[Qemu-ppc] [PATCH 3/9] target-ppc: Introduce tm_enabled Bit to CPU State |
Date: |
Thu, 18 Dec 2014 10:34:31 -0600 |
Add a bit (tm_enabled) to CPU state that mirrors the MSR[TM] bit.
This is analogous to the other "available" bits in the MSR (FP,
VSX, etc.).
NOTE: Since MSR[TM] occupies big-endian bit 31, the code is wrapped
with a PPC64 bit check.
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/translate.c | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d381632..7217041 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -203,6 +203,7 @@ typedef struct DisasContext {
int altivec_enabled;
int vsx_enabled;
int spe_enabled;
+ int tm_enabled;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled;
uint64_t insns_flags;
@@ -11311,6 +11312,13 @@ static inline void
gen_intermediate_code_internal(PowerPCCPU *cpu,
} else {
ctx.vsx_enabled = 0;
}
+#if defined(TARGET_PPC64)
+ if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
+ ctx.tm_enabled = msr_tm;
+ } else {
+ ctx.tm_enabled = 0;
+ }
+#endif
if ((env->flags & POWERPC_FLAG_SE) && msr_se)
ctx.singlestep_enabled = CPU_SINGLE_STEP;
else
--
1.7.1
[Qemu-ppc] [PATCH 6/9] target-ppc: Introduce tbegin, Tom Musta, 2014/12/18
[Qemu-ppc] [PATCH 7/9] target-ppc: Introduce TM Noops, Tom Musta, 2014/12/18
[Qemu-ppc] [PATCH 8/9] target-ppc: Introduce tcheck, Tom Musta, 2014/12/18