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[Qemu-ppc] [PULL 078/107] target-ppc: Add xviexpdp instruction
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 078/107] target-ppc: Add xviexpdp instruction |
Date: |
Thu, 2 Feb 2017 16:14:16 +1100 |
From: Nikunj A Dadhania <address@hidden>
xviexpdp: VSX Vector Insert Exponent Dual Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate/vsx-impl.inc.c | 26 ++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 27 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index c86f1b5..b66272e 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1370,6 +1370,32 @@ static void gen_xviexpsp(DisasContext *ctx)
tcg_temp_free_i64(t0);
}
+static void gen_xviexpdp(DisasContext *ctx)
+{
+ TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+ TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+ TCGv_i64 xah = cpu_vsrh(xA(ctx->opcode));
+ TCGv_i64 xal = cpu_vsrl(xA(ctx->opcode));
+ TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
+ TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
+ TCGv_i64 t0;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ tcg_gen_andi_i64(xth, xah, 0x800FFFFFFFFFFFFF);
+ tcg_gen_andi_i64(t0, xbh, 0x7FF);
+ tcg_gen_shli_i64(t0, t0, 52);
+ tcg_gen_or_i64(xth, xth, t0);
+ tcg_gen_andi_i64(xtl, xal, 0x800FFFFFFFFFFFFF);
+ tcg_gen_andi_i64(t0, xbl, 0x7FF);
+ tcg_gen_shli_i64(t0, t0, 52);
+ tcg_gen_or_i64(xtl, xtl, t0);
+ tcg_temp_free_i64(t0);
+}
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
diff --git a/target/ppc/translate/vsx-ops.inc.c
b/target/ppc/translate/vsx-ops.inc.c
index 93752f0..253a5c4 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -125,6 +125,7 @@ GEN_VSX_XFORM_300(xsiexpqp, 0x4, 0x1B, 0x00000001),
#endif
GEN_XX3FORM(xviexpsp, 0x00, 0x1B, PPC2_ISA300),
+GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300),
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
--
2.9.3
- [Qemu-ppc] [PULL 080/107] target-ppc: Add xvxexpdp instruction, (continued)
- [Qemu-ppc] [PULL 080/107] target-ppc: Add xvxexpdp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 095/107] spapr: clock should count only if vm is running, David Gibson, 2017/02/02
- Re: [Qemu-ppc] [Qemu-devel] [PULL 095/107] spapr: clock should count only if vm is running, Mark Cave-Ayland, 2017/02/02
- Re: [Qemu-ppc] [Qemu-devel] [PULL 095/107] spapr: clock should count only if vm is running, Laurent Vivier, 2017/02/02
- Re: [Qemu-ppc] [Qemu-devel] [PULL 095/107] spapr: clock should count only if vm is running, Mark Cave-Ayland, 2017/02/02
- Re: [Qemu-ppc] [Qemu-devel] [PULL 095/107] spapr: clock should count only if vm is running, Laurent Vivier, 2017/02/02
- Re: [Qemu-ppc] [Qemu-devel] [PULL 095/107] spapr: clock should count only if vm is running, Mark Cave-Ayland, 2017/02/02
- Re: [Qemu-ppc] [Qemu-devel] [PULL 095/107] spapr: clock should count only if vm is running, Laurent Vivier, 2017/02/07
- Re: [Qemu-ppc] [Qemu-devel] [PULL 095/107] spapr: clock should count only if vm is running, Mark Cave-Ayland, 2017/02/09
- Re: [Qemu-ppc] [Qemu-devel] [PULL 095/107] spapr: clock should count only if vm is running, Laurent Vivier, 2017/02/09
[Qemu-ppc] [PULL 078/107] target-ppc: Add xviexpdp instruction,
David Gibson <=
[Qemu-ppc] [PULL 081/107] target-ppc: Add xvxsigsp instruction, David Gibson, 2017/02/02
[Qemu-ppc] [PULL 084/107] ppc/prep: update MAINTAINERS file, David Gibson, 2017/02/02
[Qemu-ppc] [PULL 085/107] ppc: Implement bcdtrunc. instruction, David Gibson, 2017/02/02
[Qemu-ppc] [PULL 101/107] target-ppc: Add xststdc[sp, dp, qp] instructions, David Gibson, 2017/02/02
[Qemu-ppc] [PULL 106/107] ppc/kvm: Handle the "family" CPU via alias instead of registering new types, David Gibson, 2017/02/02
Re: [Qemu-ppc] [Qemu-devel] [PULL 000/107] ppc-for-2.9 queue 20170202, no-reply, 2017/02/02