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[Qemu-ppc] [PATCH V5 1/9] target/ppc/POWER9: Add ISAv3.00 MMU definition
From: |
Suraj Jitindar Singh |
Subject: |
[Qemu-ppc] [PATCH V5 1/9] target/ppc/POWER9: Add ISAv3.00 MMU definition |
Date: |
Wed, 1 Mar 2017 17:54:33 +1100 |
POWER9 processors implement the mmu as defined in version 3.00 of the ISA.
Add a definition for this mmu model and set the POWER9 cpu model to use
this mmu model.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Acked-by: Balbir Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
---
V4 -> V5:
- Nothing
V3 -> V4:
- Add POWERPC_MMU_V3 flag to mmu model
---
target/ppc/cpu-qom.h | 7 ++++++-
target/ppc/mmu_helper.c | 2 ++
target/ppc/translate_init.c | 3 +--
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index b7977ba..da7eb5a 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -71,6 +71,7 @@ enum powerpc_mmu_t {
#define POWERPC_MMU_1TSEG 0x00020000
#define POWERPC_MMU_AMR 0x00040000
#define POWERPC_MMU_64K 0x00080000
+#define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
/* 64 bits PowerPC MMU */
POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
/* Architecture 2.03 and later (has LPCR) */
@@ -86,10 +87,14 @@ enum powerpc_mmu_t {
POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
| POWERPC_MMU_64K
| POWERPC_MMU_AMR | 0x00000004,
- /* FIXME Add POWERPC_MMU_3_OO defines */
/* Architecture 2.07 "degraded" (no 1T segments) */
POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR
| 0x00000004,
+ /* Architecture 3.00 variant */
+ POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
+ | POWERPC_MMU_64K
+ | POWERPC_MMU_AMR | POWERPC_MMU_V3
+ | 0x00000005,
};
/*****************************************************************************/
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index e22ddc3..a1af3d6 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -1940,6 +1940,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
case POWERPC_MMU_2_06a:
case POWERPC_MMU_2_07:
case POWERPC_MMU_2_07a:
+ case POWERPC_MMU_3_00:
#endif /* defined(TARGET_PPC64) */
env->tlb_need_flush = 0;
tlb_flush(CPU(cpu));
@@ -1979,6 +1980,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env,
target_ulong addr)
case POWERPC_MMU_2_06a:
case POWERPC_MMU_2_07:
case POWERPC_MMU_2_07a:
+ case POWERPC_MMU_3_00:
/* tlbie invalidate TLBs for all segments */
/* XXX: given the fact that there are too many segments to invalidate,
* and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 3c839bd..c95c9cd 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8828,8 +8828,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
- /* Using 2.07 defines until new radix model is added. */
- pcc->mmu_model = POWERPC_MMU_2_07;
+ pcc->mmu_model = POWERPC_MMU_3_00;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
/* segment page size remain the same */
--
2.5.5
- [Qemu-ppc] [PATCH V5 0/9] target/ppc: Implement POWER9 pseries TCG legacy support, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 1/9] target/ppc/POWER9: Add ISAv3.00 MMU definition,
Suraj Jitindar Singh <=
- [Qemu-ppc] [PATCH V5 2/9] target/ppc/POWER9: Adapt LPCR handling for POWER9, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 3/9] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 4/9] target/ppc: Add patb_entry to sPAPRMachineState, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 6/9] target/ppc/POWER9: Add POWER9 mmu fault handler, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 5/9] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 7/9] target/ppc/POWER9: Add POWER9 pa-features definition, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 8/9] target/ppc/POWER9: Add cpu_has_work function for POWER9, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 9/9] hw/ppc/spapr: Add POWER9 to pseries cpu models, Suraj Jitindar Singh, 2017/03/01
- Re: [Qemu-ppc] [PATCH V5 0/9] target/ppc: Implement POWER9 pseries TCG legacy support, David Gibson, 2017/03/01