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[Qemu-ppc] [PATCH V5 7/9] target/ppc/POWER9: Add POWER9 pa-features defi
From: |
Suraj Jitindar Singh |
Subject: |
[Qemu-ppc] [PATCH V5 7/9] target/ppc/POWER9: Add POWER9 pa-features definition |
Date: |
Wed, 1 Mar 2017 17:54:39 +1100 |
Add a pa-features definition which includes all of the new fields which
have been added, note we don't claim support for any of these new features
at this stage.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Acked-by: Balbir Singh <address@hidden>
---
hw/ppc/spapr.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 8bab415..c141129 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -356,6 +356,20 @@ static void spapr_populate_pa_features(CPUPPCState *env,
void *fdt, int offset)
0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
+ /* Currently we don't advertise any of the "new" ISAv3.00 functionality */
+ uint8_t pa_features_300[] = { 64, 0,
+ 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
+ 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 24 - 29 */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 30 - 35 */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 36 - 41 */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 42 - 47 */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 48 - 53 */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 54 - 59 */
+ 0x00, 0x00, 0x00, 0x00 }; /* 60 - 63 */
+
uint8_t *pa_features;
size_t pa_size;
@@ -370,6 +384,10 @@ static void spapr_populate_pa_features(CPUPPCState *env,
void *fdt, int offset)
pa_features = pa_features_207;
pa_size = sizeof(pa_features_207);
break;
+ case POWERPC_MMU_3_00:
+ pa_features = pa_features_300;
+ pa_size = sizeof(pa_features_300);
+ break;
default:
return;
}
--
2.5.5
- [Qemu-ppc] [PATCH V5 0/9] target/ppc: Implement POWER9 pseries TCG legacy support, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 1/9] target/ppc/POWER9: Add ISAv3.00 MMU definition, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 2/9] target/ppc/POWER9: Adapt LPCR handling for POWER9, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 3/9] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 4/9] target/ppc: Add patb_entry to sPAPRMachineState, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 6/9] target/ppc/POWER9: Add POWER9 mmu fault handler, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 5/9] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 7/9] target/ppc/POWER9: Add POWER9 pa-features definition,
Suraj Jitindar Singh <=
- [Qemu-ppc] [PATCH V5 8/9] target/ppc/POWER9: Add cpu_has_work function for POWER9, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 9/9] hw/ppc/spapr: Add POWER9 to pseries cpu models, Suraj Jitindar Singh, 2017/03/01
- Re: [Qemu-ppc] [PATCH V5 0/9] target/ppc: Implement POWER9 pseries TCG legacy support, David Gibson, 2017/03/01