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[Qemu-ppc] [PULL 1/6] booke206: fix MAS update on tlb miss
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 1/6] booke206: fix MAS update on tlb miss |
Date: |
Wed, 9 Aug 2017 17:03:52 +1000 |
From: KONRAD Frederic <address@hidden>
When a tlb instruction miss happen, rw is set to 0 at the bottom
of cpu_ppc_handle_mmu_fault which cause the MAS update function to miss
the SAS and TS bit in MAS6, MAS1 in booke206_update_mas_tlb_miss.
Just calling booke206_update_mas_tlb_miss with rw = 2 solve the issue.
Signed-off-by: KONRAD Frederic <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/mmu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index b7b9088842..f06b9382b4 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -1551,7 +1551,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env,
target_ulong address,
env->spr[SPR_40x_ESR] = 0x00000000;
break;
case POWERPC_MMU_BOOKE206:
- booke206_update_mas_tlb_miss(env, address, rw);
+ booke206_update_mas_tlb_miss(env, address, 2);
/* fall through */
case POWERPC_MMU_BOOKE:
cs->exception_index = POWERPC_EXCP_ITLB;
--
2.13.4
- [Qemu-ppc] [PULL 0/6] ppc patch queue 2017-08-09, David Gibson, 2017/08/09
- [Qemu-ppc] [PULL 3/6] target/ppc: Implement TIDR, David Gibson, 2017/08/09
- [Qemu-ppc] [PULL 1/6] booke206: fix MAS update on tlb miss,
David Gibson <=
- [Qemu-ppc] [PULL 5/6] spapr_drc: abort if object_property_add_child() fails, David Gibson, 2017/08/09
- [Qemu-ppc] [PULL 6/6] spapr: Fix bug in h_signal_sys_reset(), David Gibson, 2017/08/09
- [Qemu-ppc] [PULL 4/6] target/ppc: Add stub implementation of the PSSCR, David Gibson, 2017/08/09
- [Qemu-ppc] [PULL 2/6] ppc: fix double-free in cpu_post_load(), David Gibson, 2017/08/09
- Re: [Qemu-ppc] [PULL 0/6] ppc patch queue 2017-08-09, Peter Maydell, 2017/08/10