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[Qemu-ppc] [PULL 17/22] ppc/pnv: change core mask for POWER9
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 17/22] ppc/pnv: change core mask for POWER9 |
Date: |
Wed, 17 Jan 2018 13:25:20 +1100 |
From: Cédric Le Goater <address@hidden>
When addressed by XSCOM, the first core has the 0x20 chiplet ID but
the CPU PIR can start at 0x0.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv.c | 4 ++--
tests/pnv-xscom-test.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 536162b274..f9591cd41d 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -707,9 +707,9 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip,
uint32_t core_id)
#define POWER8_CORE_MASK (0x7e7eull)
/*
- * POWER9 has 24 cores, ids starting at 0x20
+ * POWER9 has 24 cores, ids starting at 0x0
*/
-#define POWER9_CORE_MASK (0xffffff00000000ull)
+#define POWER9_CORE_MASK (0xffffffffffffffull)
static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
{
diff --git a/tests/pnv-xscom-test.c b/tests/pnv-xscom-test.c
index a1a119c091..9d545c4718 100644
--- a/tests/pnv-xscom-test.c
+++ b/tests/pnv-xscom-test.c
@@ -49,7 +49,7 @@ static const PnvChip pnv_chips[] = {
.xscom_base = 0x000603fc00000000ull,
.xscom_core_base = 0x0ull,
.cfam_id = 0x220d104900008000ull,
- .first_core = 0x20,
+ .first_core = 0x0,
},
#endif
};
--
2.14.3
- [Qemu-ppc] [PULL 00/22] ppc-for-2.12 queue 20180117, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 04/22] spapr: Validate capabilities on migration, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 21/22] target/ppc: add support for POWER9 HILE, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 09/22] spapr: Remove unnecessary 'options' field from sPAPRCapabilityInfo, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 07/22] spapr: Handle Decimal Floating Point (DFP) as an optional capability, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 06/22] spapr: Handle VMX/VSX presence as an spapr capability flag, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 03/22] spapr: Treat Hardware Transactional Memory (HTM) as an optional capability, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 18/22] ppc/pnv: introduce pnv*_is_power9() helpers, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 17/22] ppc/pnv: change core mask for POWER9,
David Gibson <=
- [Qemu-ppc] [PULL 13/22] spapr: Adjust default VSMT value for better migration compatibility, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 12/22] spapr: Allow some cases where we can't set VSMT mode in the kernel, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 02/22] spapr: Capabilities infrastructure, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 22/22] target-ppc: Fix booke206 tlbwe TLB instruction, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 19/22] ppc/pnv: fix XSCOM core addressing on POWER9, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 01/22] target/ppc: Yet another fix for KVM-HV HPTE accessors, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 10/22] ppc: Change Power9 compat table to support at most 8 threads/core, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 05/22] target/ppc: Clean up probing of VMX, VSX and DFP availability on KVM, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 11/22] target/ppc: Clarify compat mode max_threads value, David Gibson, 2018/01/16
- [Qemu-ppc] [PULL 20/22] ppc/pnv: change initrd address, David Gibson, 2018/01/16