Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 16/35] target/riscv: Convert RV

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Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 16/35] target/riscv: Convert RV

From:	Bastian Koppelmann
Subject:	Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 16/35] target/riscv: Convert RV priv insns to decodetree
Date:	Fri, 15 Feb 2019 13:13:49 +0100
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.0


On 2/13/19 4:53 PM, Palmer Dabbelt wrote:

+}
+
+static bool trans_sret(DisasContext *ctx, arg_sret *a)
+{
+#ifndef CONFIG_USER_ONLY
+    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+
+    if (riscv_has_ext(ctx->env, RVS)) {



This should use has_ext()

Cheers,

Bastian

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[Qemu-riscv] [PATCH v7 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, (continued)
- [Qemu-riscv] [PATCH v7 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 26/35] target/riscv: Remove shift and slt insn manual decoding, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 12/35] target/riscv: Convert RV32F insns to decodetree, Palmer Dabbelt, 2019/02/13
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 12/35] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2019/02/15
- [Qemu-riscv] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Palmer Dabbelt, 2019/02/13
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Bastian Koppelmann, 2019/02/13
- [Qemu-riscv] [PATCH v7 28/35] target/riscv: Rename trans_arith to gen_arith, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 30/35] target/riscv: Remove decode_RV32_64G(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 16/35] target/riscv: Convert RV priv insns to decodetree, Palmer Dabbelt, 2019/02/13
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 16/35] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann <=
- [Qemu-riscv] [PATCH v7 31/35] target/riscv: Convert @cs_2 insns to share translation functions, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 27/35] target/riscv: Remove manual decoding of RV32/64M insn, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 14/35] target/riscv: Convert RV32D insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Palmer Dabbelt, 2019/02/13
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15

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