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Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to
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Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree |
Date: |
Fri, 15 Feb 2019 07:14:01 -0800 (PST) |
Patchew URL: https://patchew.org/QEMU/address@hidden/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: address@hidden
Subject: [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/address@hidden -> patchew/address@hidden
t [tag update] patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
41749753bc target/riscv: Remaining rvc insn reuse 32 bit translators
024596dd05 target/riscv: Splice remaining compressed insn pairs for riscv32 vs
riscv64
e9e182931c target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
58fa40505c target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
e3db55993f target/riscv: Convert @cs_2 insns to share translation functions
d1d2029ff2 target/riscv: Remove decode_RV32_64G()
a9fe5a25ea target/riscv: Remove gen_system()
803dc342db target/riscv: Rename trans_arith to gen_arith
a88849bcbb target/riscv: Remove manual decoding of RV32/64M insn
b961dec542 target/riscv: Remove shift and slt insn manual decoding
e11ca6b00d target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
90c517aabb target/riscv: Move gen_arith_imm() decoding into trans_* functions
deeec4309d target/riscv: Remove manual decoding from gen_store()
7143c951e9 target/riscv: Remove manual decoding from gen_load()
32d027745f target/riscv: Remove manual decoding from gen_branch()
589cff707b target/riscv: Remove gen_jalr()
918f53165b target/riscv: Convert quadrant 2 of RVXC insns to decodetree
a1be693016 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
904263fad2 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
50fa542e07 target/riscv: Convert RV priv insns to decodetree
d0c5997811 target/riscv: Convert RV64D insns to decodetree
0b7e3a3c7e target/riscv: Convert RV32D insns to decodetree
e99251e477 target/riscv: Convert RV64F insns to decodetree
dcdcc961d7 target/riscv: Convert RV32F insns to decodetree
ad63f7f324 target/riscv: Convert RV64A insns to decodetree
30c0cd80b6 target/riscv: Convert RV32A insns to decodetree
7a5fde3c87 target/riscv: Convert RVXM insns to decodetree
cc4a27b930 target/riscv: Convert RVXI csr insns to decodetree
5795125296 target/riscv: Convert RVXI fence insns to decodetree
2f54263ec3 target/riscv: Convert RVXI arithmetic insns to decodetree
a05e71e427 target/riscv: Convert RV64I load/store insns to decodetree
d243b94bba target/riscv: Convert RV32I load/store insns to decodetree
862ba6525c target/riscv: Convert RVXI branch insns to decodetree
7387d5d18f target/riscv: Activate decodetree and implemnt LUI & AUIPC
171e78f1b0 target/riscv: Move CPURISCVState pointer to DisasContext
=== OUTPUT BEGIN ===
1/35 Checking commit 171e78f1b033 (target/riscv: Move CPURISCVState pointer to
DisasContext)
2/35 Checking commit 7387d5d18ff2 (target/riscv: Activate decodetree and
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1885:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 2/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/35 Checking commit 862ba6525ca2 (target/riscv: Convert RVXI branch insns to
decodetree)
4/35 Checking commit d243b94bba3f (target/riscv: Convert RV32I load/store insns
to decodetree)
5/35 Checking commit a05e71e427dc (target/riscv: Convert RV64I load/store insns
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 5/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 2f54263ec39e (target/riscv: Convert RVXI arithmetic insns
to decodetree)
7/35 Checking commit 5795125296da (target/riscv: Convert RVXI fence insns to
decodetree)
8/35 Checking commit cc4a27b93012 (target/riscv: Convert RVXI csr insns to
decodetree)
9/35 Checking commit 7a5fde3c8795 (target/riscv: Convert RVXM insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 145 lines checked
Patch 9/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 30c0cd80b672 (target/riscv: Convert RV32A insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 188 lines checked
Patch 10/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit ad63f7f32406 (target/riscv: Convert RV64A insns to
decodetree)
12/35 Checking commit dcdcc961d738 (target/riscv: Convert RV32F insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 416 lines checked
Patch 12/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit e99251e477e7 (target/riscv: Convert RV64F insns to
decodetree)
14/35 Checking commit 0b7e3a3c7ead (target/riscv: Convert RV32D insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 373 lines checked
Patch 14/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit d0c59978112c (target/riscv: Convert RV64D insns to
decodetree)
16/35 Checking commit 50fa542e0783 (target/riscv: Convert RV priv insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 16/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 904263fad2c6 (target/riscv: Convert quadrant 0 of RVXC
insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:1067:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 227 lines checked
Patch 17/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/35 Checking commit a1be693016f7 (target/riscv: Convert quadrant 1 of RVXC
insns to decodetree)
19/35 Checking commit 918f53165b7b (target/riscv: Convert quadrant 2 of RVXC
insns to decodetree)
20/35 Checking commit 589cff707b03 (target/riscv: Remove gen_jalr())
21/35 Checking commit 32d027745f74 (target/riscv: Remove manual decoding from
gen_branch())
22/35 Checking commit 7143c951e9b5 (target/riscv: Remove manual decoding from
gen_load())
23/35 Checking commit deeec4309dcf (target/riscv: Remove manual decoding from
gen_store())
24/35 Checking commit 90c517aabb01 (target/riscv: Move gen_arith_imm() decoding
into trans_* functions)
25/35 Checking commit e11ca6b00db3 (target/riscv: make ADD/SUB/OR/XOR/AND insn
use arg lists)
26/35 Checking commit b961dec54274 (target/riscv: Remove shift and slt insn
manual decoding)
27/35 Checking commit a88849bcbbca (target/riscv: Remove manual decoding of
RV32/64M insn)
28/35 Checking commit 803dc342db68 (target/riscv: Rename trans_arith to
gen_arith)
29/35 Checking commit a9fe5a25eacb (target/riscv: Remove gen_system())
30/35 Checking commit d1d2029ff220 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit e3db55993f1c (target/riscv: Convert @cs_2 insns to share
translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:543:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 31/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
32/35 Checking commit 58fa40505cd3 (target/riscv: Convert @cl_d, @cl_w, @cs_d,
@cs_w insns)
33/35 Checking commit e9e182931cf6 (target/riscv: Splice fsw_sd and flw_ld for
riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 309 lines checked
Patch 33/35 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 024596dd0512 (target/riscv: Splice remaining compressed
insn pairs for riscv32 vs riscv64)
35/35 Checking commit 41749753bc27 (target/riscv: Remaining rvc insn reuse 32
bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to address@hidden
- [Qemu-riscv] [PATCH v7 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, (continued)
- [Qemu-riscv] [PATCH v7 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Palmer Dabbelt, 2019/02/13
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, Bastian Koppelmann, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree,
no-reply <=
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, Bastian Koppelmann, 2019/02/20