[Simulavr-devel] using simulavrxx for real work :)

[Joel Sherrill]

Hi,

For those who don't know why I got involved in simulavr,
here goes.  I tried it months ago to use to debug the
RTEMS AVR port.  That was strictly an on my own time
effort and I couldn't get anywhere with it in "free time."
I still want to do that but it competes with my other
RTEMS "volunteer time".

This time I am trying to use simulavrxx as the core
of test system for a real application.  Obviously,
it had to build to make that possible.  I now think
I am ready to move on to examining which atmega128
features the application is using that are missing.

So I hope I can now ask more AVR detailed questions
in the near future for those more familiar with
simulavrxx and the AVR. And start hitting those
1.0 items. :)

This is my first round of questions from this
perspective:

(1) Right now, it looks like the simulator doesn't
do anything if you access a non-existent port/address.
Is this right?  If so, wouldn't it be desirable to
print a message?

I ask because I can run the end user application on
simulavrxx.  The simulator is not dying but it would
be nice to know when we access a device/register that
isn't implemented.  I am doing a code audit to identify
what AVR features are used but having the simulator
smack my hand when something isn't implemented or
there would be nice.

(2) What is the proper way to print the current
instruction address?  I ask because when I run the
application on the simulator, the only output I get is
"spsr is read only!" and it would be nice to get a better
hint. :)

(3) Could someone tell me what the information
printed when I do a <ctl>-C to kill the run means?
Output is attached.

Thanks. 

--
Joel Sherrill, Ph.D.             Director of Research & Development
address@hidden        On-Line Applications Research
Ask me about RTEMS: a free RTOS  Huntsville AL 35805
  Support Available             (256) 722-9985


$ ../b-sim/src/simulavr -d atmega128 -f app.elf
spsr is read only! ^CSystemClock::Endless stopped
number of cpu cycles simulated: 14485916
IRQ STATISTIC
        FlagSet flagCleared     HandlerStarted  HandlerFinished Set->Clear      
Set->Started    Set->Finished   Started->Finished
Core: app.elf
Statistic for vector: 0x9
Set->Clear >    931279750       931280000       931281000       931293500       
250     1250    13750   12500   
Set->Clear <    927599750       927599750       927600250       927612750       
0       500     13000   12500   
Set->HandlerStarted >   931279750       931280000       931281000       
931293500       250     1250    13750   12500   
Set->HandlerStarted <   927599750       927599750       927600250       
927612750       0       500     13000   12500   
Set->HandlerFinished >  931279750       931280000       931281000       
931293500       250     1250    13750   12500   
Set->HandlerFinished <  927599750       927599750       927600250       
927612750       0       500     13000   12500   
Handler Start->Finished >       927599750       927599750       927600250       
927612750       0       500     13000   12500   
Handler Start->Finished <       927599750       927599750       927600250       
927612750       0       500     13000   12500