Re: [Simulavr-devel] atmega168 thoroughness

[Petr Hluzín]

On 27 February 2011 00:25, Michael Hennebry
<address@hidden> wrote:
> How thorough is the simulation of atmega168s and their siblings?
> For example, some of the code I would like to test depends on
> an assignment to SPDR changing MISO even when SCK isn't changing.

AVR151: Setup And Use of The SPI:
"When the SPI is configured as a slave, the transmission starts with
the falling edge of the SS
line. This activates the SPI of the slave and the MSB of the byte
stored in its data registe
(SPDR) is output on the MISO line. The actual transfer is started by a
software write to the
SPDR of the master. ..."
"A write collision occurs if the SPDR is written while a transfer is
in progress. ..."

Do you mean that?

I think that from slave's point of view the transfers starts "with the
falling edge of the SS". Therefore when the first bit appears on MISO
line the slave transmission is already in progress and writing to SPDR
will cause a collision (WCOL bit in SPSR). Write by master will just
start the clocking.

This is what simulavr does (the collision flag). When you write SPDR
it does not change MISO line. (It is a HWSpi::spdr_access() function.)

(Take this with a grain of salt. I have never used SPI before.)

-- 
Petr Hluzin