Re: [Simulavr-devel] atmega168 thoroughness

[Michael Hennebry]

On Sun, 27 Feb 2011, Petr Hluzín wrote:

> On 27 February 2011 00:25, Michael Hennebry
> <address@hidden> wrote:
> > How thorough is the simulation of atmega168s and their siblings?
> > For example, some of the code I would like to test depends on
> > an assignment to SPDR changing MISO even when SCK isn't changing.
>
> AVR151: Setup And Use of The SPI:
> "When the SPI is configured as a slave, the transmission starts with
> the falling edge of the SS
> line. This activates the SPI of the slave and the MSB of the byte
> stored in its data registe
> (SPDR) is output on the MISO line. The actual transfer is started by a
> software write to the
> SPDR of the master. ..."
> "A write collision occurs if the SPDR is written while a transfer is
> in progress. ..."

I think that AVR151 is making a distinction
between transmission and transfer.

> Do you mean that?
>
> I think that from slave's point of view the transfers starts "with the
> falling edge of the SS". Therefore when the first bit appears on MISO
> line the slave transmission is already in progress and writing to SPDR
> will cause a collision (WCOL bit in SPSR). Write by master will just
> start the clocking.

> From the data sheet, collisions only happen during transfer.
A slave assigning to SPDR during transmission
but before or after transfer will wiggle MISO.

I've used this on actual hardware to have the slave signal the master that
it had received a byte and sending another would not overwrite unread data.

Would it work on simulavr?

> This is what simulavr does (the collision flag). When you write SPDR
> it does not change MISO line. (It is a HWSpi::spdr_access() function.)
>
> (Take this with a grain of salt. I have never used SPI before.)

--
Michael   address@hidden
"Pessimist: The glass is half empty.
Optimist:   The glass is half full.
Engineer:   The glass is twice as big as it needs to be."