Re: [Simulavr-devel] attiny85 - external interrupt support (INT0/PCINT)

[Thomas K]

Hi

should work. Message means, that there are no registers assigned but 
code shows (gimsk and mcucr) Do you really simulate attiny85? E.g. start 
simulavr with "-d attiny85"? What version simulavr do you use? (if self 
compiled, from where do us download the code?)

cu, Thomas

Am 03.02.2016 um 10:35 schrieb zid:
> Hi,
>
> I am trying to simulate external interrupts (INT0) on an ATTiny85.
>
> After adding the following lines, I get the following errors:
>
> // Enable INT0 interupt
> GIMSK |= (1<<INT0);
>
> // Set INT0 interupt to rising edge detection
> MCUCR |= (1<<ISC00) | (1<<ISC01);
>
>
> WARNING: file rwmem.cpp: line 222: Invalid read access from IO[0x5b],
> PC=0x80
> WARNING: file rwmem.cpp: line 231: Invalid write access to IO[0x5b]=0x40,
> PC=0x84
> WARNING: file rwmem.cpp: line 222: Invalid read access from IO[0x55],
> PC=0x86
> WARNING: file rwmem.cpp: line 231: Invalid write access to IO[0x55]=0x3,
> PC=0x8a
>
>
> Does this just mean this feature is not available to simulate on this MCU?
> Or am I missing something fundamental?
>
> Thanks
> Zid
>
>
>
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