Re: [Simulavr-devel] attiny85 - external interrupt support (INT0/PCINT)

[Thomas K]

Hi,

Klaus is right! I was looking in __my__ repo and there 0x55 and 0x5b are 
supported. :-)

So, the right answer is: in the moment not supported! But will come next 
- I hope. :-) USI feature is running for SPI and TWI slave in the 
moment. I think, this is 70% finished.

Maybe I'll extract changes to support this 2 registers ...

cu, Thomas


Am 04.02.2016 um 08:12 schrieb Klaus Rudolph:
> Hi,
>
> > WARNING: file rwmem.cpp: line 222: Invalid read access from IO[0x5b],
> > PC=0x80
> > WARNING: file rwmem.cpp: line 231: Invalid write access to IO[0x5b]=0x40,
> > PC=0x84
> > WARNING: file rwmem.cpp: line 222: Invalid read access from IO[0x55],
> > PC=0x86
> > WARNING: file rwmem.cpp: line 231: Invalid write access to IO[0x55]=0x3,
> > PC=0x8a
> >
> >
> > Does this just mean this feature is not available to simulate on this MCU?
> > Or am I missing something fundamental?
> A short view in the source: src/attiny25_45_85.cpp:
>
> 131     //rw[0x5c] reserved
> 132     //rw[0x5b] reserved
> 133     //rw[0x5a] reserved
> 134     rw[0x59]= & timer01irq->timsk_reg;
> 135     rw[0x58]= & timer01irq->tifr_reg;
> 136     //rw[0x57] reserved
> 137     //rw[0x56] reserved
> 138     //rw[0x55] reserved
> 139     //rw[0x54] reserved
>
> Sorry, currently not supported.
>
> Regards
>   Klaus
>
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