[avr-chat] Pushing the limits of the ADC

[Andreas Stemmer]

I have a project (using ATmega8 TQFP) where I need all eight ADC
channels with high sample rate. I use a 16 MHz crystal and the datasheet
recommends a ADC clock frequency of 50 kHz to 200 kHz, so I have to set
the prescaler to 128. This gives me a clock rate of 125 kHz and
therefore a maximum sample rate of about 1.2 kHz for each channel. I'd
like to have it faster (basically as fast as possible, but 2 kHz would
be a good start).

The datasheet says: "If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200 kHz to get a
higher sample rate."

I don't understand what the practical effect of a higher clock rate
would be. As the ADC works by successive approximation, I could
understand that it would perhaps be possible to save a few clock cycles
if I didn't wait for the last bits (if hardware allowed it). But by
increasing the clock rate, I have the impression that the DAC is running
out of spec and anything could happen...

So my question is: what are the practical effects of a clock rate of
let's say 250 kHz or even more for the ADC and has anybody tried and
used it already?

Thank you,
Andreas