Re: [avr-chat] Pushing the limits of the ADC

[Graham Davies]

Andreas Stemmer wrote:
> ...: what are the practical effects of a [high ADC] clock rate ...

I can answer from a theoretical viewpoint, i.e. without reference to Atmel's 
particular implementation.

A successive approximation A-to-D works by "guessing" each bit, starting 
with the most significant, applying the guess so far to a D-to-A and 
comparing the output to the value to be converted.  Depending on the output 
of the comparator, the previously guessed bit is either retained or flipped 
and the next bit down is guessed.  This is like guessing a number when the 
person who knows the answer tells you only whether your guess is larger than 
the number or equal/smaller.

The main limiting factor for speed is the settling time of the D-to-A and 
comparator.  If you terminate a bit period too soon by clocking too fast, 
you may not get a true comparison of the current guess and the value to be 
converted because the D-to-A output and the comparator are still changing. 
This effect is at its worst when you're working on the most significant bits 
because then the D-to-A output swings are largest.  If you incorrectly guess 
the most significant bit, it doesn't mean that's how far off the result will 
be because the rest of the bits will make up for the bad guess as far as 
possible.  So, you might get something like 01111111 when the correct result 
would be 10000110.

So, as Atmel say, by clocking too fast you will lose accuracy.  Errors won't 
be uniform over the conversion codes but will be clustered near the most 
significant bit transitions.  You will probably be able to offset this 
problem somewhat by only applying inputs of up to VREF/4, say, so that the 
most significant two bits are always zero and you have just 8 bits left. 
The D-to-A will then only be called upon to swing over one quarter of its 
full range.

Graham.