Re: urgent help on Makefile

[Paul D. Smith]

%% Yin Lei <address@hidden> writes:

  yl>   for each target, create a file named as $(target name).list
  yl>   in this file, I can put the list of source codes.
  yl>   In Makefile, there is a macro named as "MODULE_LIST", which
  yl>   contains the list of my targets. I hope that Makefile can
  yl>   check the source codes for each target automatically.

  yl> $(MODULE_LIST):%:
  yl>   override MODULE_SOURCE = $(sort $(filter-out /%, $(shell cat \
  yl>                            $*.list)))
  yl>   override MODULE_OBJS   = $(MODULE_SOURCE:%.c=%.o)

This can't work, because you can't put make commands (like variable
assignments) inside a command script.  The command script is passed to
the shell and run there, and make syntax is (except by accident) not
valid there.

Even if it were, values set in a subprocess like a shell cannot affect
the parent process.

Plus, this is broken in other ways.

  yl> could you please tell me how to do it?

There are several ways.  However, there are no perfect ways.  The
simplest, if you're willing to do it, is put the prerequisites in the
project makefiles themselves; something like:

  MODULE_LIST = proj1 proj2 proj3

  include $(MODULE_LIST:%=%.mk)

  $(MODULE_LIST):
        <do whatever to build a module>

Then in each proj1.mk, proj2.mk, proj3.mk, etc. you'd have:

  SRCS = foo.c bar.c baz.c

  proj1: $(SRCS:.c=.o)

If you're not willing to put the prerequisite into the project makefile,
then there are other things you can do.

-- 
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 Paul D. Smith <address@hidden>          Find some GNU make tips at:
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