Re: urgent help on Makefile

[Yin Lei]

On Sun, 6 May 2001, Paul D. Smith wrote:

> This can't work, because you can't put make commands (like variable
> assignments) inside a command script.  The command script is passed to
> the shell and run there,

Thanks a lot, Paul. :)

Actually, in version 3.79 or above, It's so called "Target-specific
variable assignment" and it works. Have a look of following codes please:

=====================================================================
MODULE_LIST     = $(subst mods.,,$(notdir $(wildcard module/mods.*)))

all:    $(MODULE_LIST)

$(MODULE_LIST):%:
        override MOD_SUBDIRS    = $(sort $(filter-out /%,\
                                $(shell cat module/mods.$*)))
        override MOD_ARCH_FILES = $(foreach file,$(MODULE_SUBDIRS), \
                                src/$(file)/$(ARCH)/$(notdir $(file)))
        override MOD_ARCH_OBJS  = $(MOD_ARCH_FILES:%=%.o)

$(MODULE_LIST):%:
        @echo 'making $* ...'
        for subdir in $(MOD_SUBDIRS) ; do \
            $(MAKE) -c src/$$subdir; \
        done ; \
        $(LINK) .... -o $*

-----
if there is two module definitions:
        proj1:  sa, sb
        proj2:  sc, sd
the output will be:

making proj1...
for subdir in sa sb do ; \
    make -c src/$(subdir) ; \
done ; \
gcc .... -o proj1

making proj2...
for subdir in sc sd do ; \
    make -c src/$(subdir) ; \
done ; \
gcc ... -o proj2

====================================================================
In fact, this way is not good because there is no dependent rule
for making objective files, except write a seperate makefile for
each sub-directories. And in this makefile, if there is anything
wrong in sub-directory, the make will keep going. So it is hardly
for locating error.


>
> Even if it were, values set in a subprocess like a shell cannot affect
> the parent process.

Yes, exactly as what you said. :) sigh. This is the problem.


> Plus, this is broken in other ways.
>
>   yl> could you please tell me how to do it?
>
> There are several ways.  However, there are no perfect ways.  The
> simplest, if you're willing to do it, is put the prerequisites in the
> project makefiles themselves; something like:
>
>   MODULE_LIST = proj1 proj2 proj3
>
>   include $(MODULE_LIST:%=%.mk)
>
>   $(MODULE_LIST):
>         <do whatever to build a module>
>
> Then in each proj1.mk, proj2.mk, proj3.mk, etc. you'd have:
>
>   SRCS = foo.c bar.c baz.c
>
>   proj1: $(SRCS:.c=.o)
>
> If you're not willing to put the prerequisite into the project makefile,
> then there are other things you can do.

Yes, in my previous makefile, I wrote it in nearly same way as you
mensioned above. The problem is: when you add a new project/executable
file. you have to re-write a makefile for this project and add project
name into module list of main Makefile. It's a tedious work, and is not
user friendly.

On the other hand, this way still has problem. If you include "proj1.mk,
proj2.mk, proj3.mk", the variable "SRC" will be overrided. So I am afraid
that it will not work.


-- 
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
Lei Yin, Ph.D
Celestry Design Technologies, Inc
1982A Zanker Road, San Jose, CA 95112
Tel: (408)501-2313(O) | Fax: (408)501-2607
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
"I'd change the world but God won't give me the source code" -- Anonymous