Re: circular includes cause infinite loop

[Paul D. Smith]

%% gk <address@hidden> writes:

  g> Since I may have several makefiles with the same name 'Makefile',
  g> in different directories, I need the ifndef variable to include the
  g> full path, but I don't want to hard code the path in the makefile.

Well, typically you wouldn't run into a situation where normal makefiles
were including other normal makefiles like this.  Typically you find
"include" used to include a few well-known, generic makefiles that
provide basic environment, rules, etc. for all the other makefiles.

So you just need to protect those few, well-known makefiles.

  g> I tried prepending $(CURDIR) to the name of the makefile in the
  g> following example and still get an infinite loop.  I'm sure this is
  g> invalid syntax for ifndef

ifndef (and a few other conditional operators) didn't used to expand
their values, so you couldn't use variables in them.  This was fixed in
GNU make 3.80; from the NEWS file:

  * The argument to the "ifdef" conditional is now expanded before it's
    tested, so it can be a constructed variable name.

    Similarly, the arguments to "export" (when not used in a variable
    definition context) and "unexport" are also now expanded.

  g> but can't think of another way to do it.

All you can do is use a unique variable name in each makefile, and you
have to use it statically, not with a constructed name.

Or, require GNU make 3.80.

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