Re: [Qemu-arm] [Qemu-devel] [PATCH v4 00/31] Add ARMv8.2 half-precision functions

[no-reply]

Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: address@hidden
Subject: [Qemu-devel] [PATCH v4 00/31] Add ARMv8.2 half-precision functions

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]            patchew/address@hidden -> patchew/address@hidden
 * [new tag]               patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
760d23f344 arm/translate-a64: add all single op FP16 to handle_fp_1src_half
3ea247e123 arm/translate-a64: implement simd_scalar_three_reg_same_fp16
37e52e25c8 arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
610a2ded87 arm/translate-a64: add FP16 FMOV to simd_mod_imm
5424b22a64 arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
3e2470a1f2 arm/helper.c: re-factor rsqrte and add rsqrte_f16
f65dc9c221 arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
02a876e8b2 arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
10c2769281 arm/translate-a64: add FP16 FRECPE
99ab8acc6b arm/helper.c: re-factor recpe and add recepe_f16
16b68c0355 arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
719ccc9c2b arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
4356d7486e arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
dbbfb5f3db arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
34431e3779 arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
9fb95bb359 arm/translate-a64: initial decode for simd_two_reg_misc_fp16
ff81b5a5df arm/translate-a64: add FP16 x2 ops for simd_indexed
ea00fa8eb0 arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
87f41ae057 arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
d4787194de arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
ad7b642414 arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
cd51ab787c arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to 
simd_three_reg_same_fp16
e70d8c2a6c arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to 
simd_three_reg_same_fp16
e59dc95dc1 arm/translate-a64: initial decode for simd_three_reg_same_fp16
87ece4e0d1 arm/translate-a64: handle_3same_64 comment fix
bf53e72c06 arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
65949ff25e target/arm/helper: pass explicit fpst to set_rmode
4a2b48fb32 target/arm/cpu.h: add additional float_status flags
ca4f33ba81 target/arm/cpu.h: update comment for half-precision values
e8be261bd7 target/arm/cpu64: introduce ARM_V8_FP16 feature bit
e15c5b2b04 include/exec/helper-head.h: support f16 in helper calls

=== OUTPUT BEGIN ===
Checking PATCH 1/31: include/exec/helper-head.h: support f16 in helper calls...
Checking PATCH 2/31: target/arm/cpu64: introduce ARM_V8_FP16 feature bit...
Checking PATCH 3/31: target/arm/cpu.h: update comment for half-precision 
values...
Checking PATCH 4/31: target/arm/cpu.h: add additional float_status flags...
Checking PATCH 5/31: target/arm/helper: pass explicit fpst to set_rmode...
Checking PATCH 6/31: arm/translate-a64: implement half-precision 
F(MIN|MAX)(V|NMV)...
Checking PATCH 7/31: arm/translate-a64: handle_3same_64 comment fix...
Checking PATCH 8/31: arm/translate-a64: initial decode for 
simd_three_reg_same_fp16...
Checking PATCH 9/31: arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to 
simd_three_reg_same_fp16...
Checking PATCH 10/31: arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to 
simd_three_reg_same_fp16...
Checking PATCH 11/31: arm/translate-a64: add FP16 FMULA/X/S to 
simd_three_reg_same_fp16...
Checking PATCH 12/31: arm/translate-a64: add FP16 FR[ECP/SQRT]S to 
simd_three_reg_same_fp16...
Checking PATCH 13/31: arm/translate-a64: add FP16 pairwise ops 
simd_three_reg_same_fp16...
Checking PATCH 14/31: arm/translate-a64: add FP16 FMULX/MLS/FMLA to 
simd_indexed...
Checking PATCH 15/31: arm/translate-a64: add FP16 x2 ops for simd_indexed...
Checking PATCH 16/31: arm/translate-a64: initial decode for 
simd_two_reg_misc_fp16...
Checking PATCH 17/31: arm/translate-a64: add FP16 FPRINTx to 
simd_two_reg_misc_fp16...
Checking PATCH 18/31: arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16...
Checking PATCH 19/31: arm/translate-a64: add FP16 FCMxx (zero) to 
simd_two_reg_misc_fp16...
Checking PATCH 20/31: arm/translate-a64: add FP16 SCVTF/UCVFT to 
simd_two_reg_misc_fp16...
ERROR: space prohibited before that close parenthesis ')'
#26: FILE: target/arm/helper.c:11305:
+FLOAT_CONVS(si, h, 16, )

total: 1 errors, 0 warnings, 208 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 21/31: arm/translate-a64: add FP16 FNEG/FABS to 
simd_two_reg_misc_fp16...
Checking PATCH 22/31: arm/helper.c: re-factor recpe and add recepe_f16...
Checking PATCH 23/31: arm/translate-a64: add FP16 FRECPE...
Checking PATCH 24/31: arm/translate-a64: add FP16 FRCPX to 
simd_two_reg_misc_fp16...
Checking PATCH 25/31: arm/translate-a64: add FP16 FSQRT to 
simd_two_reg_misc_fp16...
Checking PATCH 26/31: arm/helper.c: re-factor rsqrte and add rsqrte_f16...
Checking PATCH 27/31: arm/translate-a64: add FP16 FRSQRTE to 
simd_two_reg_misc_fp16...
Checking PATCH 28/31: arm/translate-a64: add FP16 FMOV to simd_mod_imm...
Checking PATCH 29/31: arm/translate-a64: add all FP16 ops in 
simd_scalar_pairwise...
Checking PATCH 30/31: arm/translate-a64: implement 
simd_scalar_three_reg_same_fp16...
Checking PATCH 31/31: arm/translate-a64: add all single op FP16 to 
handle_fp_1src_half...
=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to address@hidden