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[Qemu-arm] [PATCH v3 02/22] target/arm: A15 PMCEID0 initialization style
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH v3 02/22] target/arm: A15 PMCEID0 initialization style nit |
Date: |
Fri, 16 Mar 2018 16:31:00 -0400 |
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 022d8c5..072cbbf 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1524,7 +1524,7 @@ static void cortex_a15_initfn(Object *obj)
cpu->id_pfr0 = 0x00001131;
cpu->id_pfr1 = 0x00011011;
cpu->id_dfr0 = 0x02010555;
- cpu->pmceid0 = 0x0000000;
+ cpu->pmceid0 = 0x00000000;
cpu->pmceid1 = 0x00000000;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x10201105;
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
[Qemu-arm] [PATCH v3 02/22] target/arm: A15 PMCEID0 initialization style nit,
Aaron Lindsay <=
[Qemu-arm] [PATCH v3 03/22] target/arm: Check PMCNTEN for whether PMCCNTR is enabled, Aaron Lindsay, 2018/03/16
[Qemu-arm] [PATCH v3 04/22] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0, Aaron Lindsay, 2018/03/16
[Qemu-arm] [PATCH v3 05/22] target/arm: Reorganize PMCCNTR read, write, sync, Aaron Lindsay, 2018/03/16
[Qemu-arm] [PATCH v3 07/22] target/arm: Fetch GICv3 state directly from CPUARMState, Aaron Lindsay, 2018/03/16
[Qemu-arm] [PATCH v3 06/22] target/arm: Mask PMU register writes based on PMCR_EL0.N, Aaron Lindsay, 2018/03/16
[Qemu-arm] [PATCH v3 08/22] target/arm: Support multiple EL change hooks, Aaron Lindsay, 2018/03/16
[Qemu-arm] [PATCH v3 10/22] target/arm: Allow EL change hooks to do IO, Aaron Lindsay, 2018/03/16