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[PATCH v7 6/9] hw/ssi: imx_spi: Disable chip selects when controller is
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v7 6/9] hw/ssi: imx_spi: Disable chip selects when controller is disabled |
Date: |
Fri, 15 Jan 2021 16:30:46 +0100 |
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
When a write to ECSPI_CONREG register to disable the SPI controller,
imx_spi_reset() is called to reset the controller, but chip select
lines should have been disabled, otherwise the state machine of any
devices (e.g.: SPI flashes) connected to the SPI master is stuck to
its last state and responds incorrectly to any follow-up commands.
Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller")
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210112145526.31095-4-bmeng.cn@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/ssi/imx_spi.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index f06bbf317e2..c132f99ba5b 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -254,6 +254,10 @@ static void imx_spi_reset(DeviceState *dev)
imx_spi_update_irq(s);
+ for (i = 0; i < ECSPI_NUM_CS; i++) {
+ qemu_set_irq(s->cs_lines[i], 1);
+ }
+
s->burst_length = 0;
}
--
2.26.2
- [PATCH v7 3/9] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value, (continued)
[PATCH v7 6/9] hw/ssi: imx_spi: Disable chip selects when controller is disabled,
Philippe Mathieu-Daudé <=
[PATCH v7 7/9] hw/ssi: imx_spi: Round up the burst length to be multiple of 8, Philippe Mathieu-Daudé, 2021/01/15
[PATCH v7 8/9] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic, Philippe Mathieu-Daudé, 2021/01/15
[PATCH v7 9/9] hw/ssi: imx_spi: Correct tx and rx fifo endianness, Philippe Mathieu-Daudé, 2021/01/15
Re: [PATCH v7 0/9] hw/ssi: imx_spi: Fix various bugs in the imx_spi model, Bin Meng, 2021/01/16