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Re: [PATCH v12 04/23] target/arm: Implement ALLINT MSR (immediate)
From: |
Peter Maydell |
Subject: |
Re: [PATCH v12 04/23] target/arm: Implement ALLINT MSR (immediate) |
Date: |
Thu, 4 Apr 2024 15:15:48 +0100 |
On Wed, 3 Apr 2024 at 11:18, Jinjie Ruan <ruanjinjie@huawei.com> wrote:
>
> Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The
> EL0 check is necessary to ALLINT, and the EL1 check is necessary when
> imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the
> unconditional write to pc and use raise_exception_ra to unwind.
>
> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- [PATCH v12 08/23] target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI, (continued)
- [PATCH v12 08/23] target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI, Jinjie Ruan, 2024/04/03
- [PATCH v12 06/23] target/arm: Add support for Non-maskable Interrupt, Jinjie Ruan, 2024/04/03
- [PATCH v12 01/23] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI, Jinjie Ruan, 2024/04/03
- [PATCH v12 10/23] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU, Jinjie Ruan, 2024/04/03
- [PATCH v12 04/23] target/arm: Implement ALLINT MSR (immediate), Jinjie Ruan, 2024/04/03
- Re: [PATCH v12 04/23] target/arm: Implement ALLINT MSR (immediate),
Peter Maydell <=
- [PATCH v12 05/23] target/arm: Support MSR access to ALLINT, Jinjie Ruan, 2024/04/03
- [PATCH v12 11/23] hw/intc/arm_gicv3: Add external IRQ lines for NMI, Jinjie Ruan, 2024/04/03
- [PATCH v12 14/23] hw/intc/arm_gicv3: Add irq non-maskable property, Jinjie Ruan, 2024/04/03
- [PATCH v12 03/23] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt, Jinjie Ruan, 2024/04/03
- [PATCH v12 13/23] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device, Jinjie Ruan, 2024/04/03
- [PATCH v12 17/23] hw/intc/arm_gicv3: Add NMI handling CPU interface registers, Jinjie Ruan, 2024/04/03