[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v12 13/23] hw/intc/arm_gicv3: Add has-nmi property to GICv3 d
From: |
Peter Maydell |
Subject: |
Re: [PATCH v12 13/23] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device |
Date: |
Fri, 5 Apr 2024 14:25:04 +0100 |
On Wed, 3 Apr 2024 at 11:18, Jinjie Ruan <ruanjinjie@huawei.com> wrote:
>
> Add a property has-nmi to the GICv3 device, and use this to set
> the NMI bit in the GICD_TYPER register. This isn't visible to
> guests yet because the property defaults to false and we won't
> set it in the board code until we've landed all of the changes
> needed to implement FEAT_GICV3_NMI.
>
> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
> index c52f060026..2d2cea6858 100644
> --- a/hw/intc/arm_gicv3_common.c
> +++ b/hw/intc/arm_gicv3_common.c
> @@ -569,6 +569,7 @@ static Property arm_gicv3_common_properties[] = {
> DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
> DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
> DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
> + DEFINE_PROP_BOOL("has-nmi", GICv3State, nmi_support, 0),
> DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn,
> 0),
> /*
> * Compatibility property: force 8 bits of physical priority, even
I was thinking about how we'll (eventually) want to handle NMI
for non-TCG cases (KVM, hvf), and I realised there's a missing
piece here: we want to make it an error to try to set has-nmi=true
for the KVM GICv3, because it doesn't support NMIs yet.
So in hw/intc/arm_gicv3_kvm.c:kvm_arm_gicv3_realize(), we want
to add a check similar to the existing "fail if s->revision != 3"
and "fail if s->security_extn" that does
if (s->nmi_support) {
error_setg(errp, "NMI is not supported with the in-kernel GIC");
return;
}
(There are some work-in-progress kernel patches for NMI support
in the in-kernel GIC, but nothing has landed yet. When it does
we'll then be able to add the support in the QEMU code.)
thanks
-- PMM
- Re: [PATCH v12 10/23] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU, (continued)
- [PATCH v12 04/23] target/arm: Implement ALLINT MSR (immediate), Jinjie Ruan, 2024/04/03
- [PATCH v12 05/23] target/arm: Support MSR access to ALLINT, Jinjie Ruan, 2024/04/03
- [PATCH v12 11/23] hw/intc/arm_gicv3: Add external IRQ lines for NMI, Jinjie Ruan, 2024/04/03
- [PATCH v12 14/23] hw/intc/arm_gicv3: Add irq non-maskable property, Jinjie Ruan, 2024/04/03
- [PATCH v12 03/23] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt, Jinjie Ruan, 2024/04/03
- [PATCH v12 13/23] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device, Jinjie Ruan, 2024/04/03
- Re: [PATCH v12 13/23] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device,
Peter Maydell <=
- [PATCH v12 17/23] hw/intc/arm_gicv3: Add NMI handling CPU interface registers, Jinjie Ruan, 2024/04/03
- [PATCH v12 21/23] hw/intc/arm_gicv3: Report the VINMI interrupt, Jinjie Ruan, 2024/04/03
- [PATCH v12 15/23] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0, Jinjie Ruan, 2024/04/03
- [PATCH v12 18/23] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read(), Jinjie Ruan, 2024/04/03
- [PATCH v12 02/23] target/arm: Add PSTATE.ALLINT, Jinjie Ruan, 2024/04/03
- [PATCH v12 19/23] hw/intc/arm_gicv3: Implement NMI interrupt priority, Jinjie Ruan, 2024/04/03
- [PATCH v12 12/23] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), Jinjie Ruan, 2024/04/03