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[PATCH 00/22] hw/riscv: sifive_u: Add missing SPI support
From: |
Bin Meng |
Subject: |
[PATCH 00/22] hw/riscv: sifive_u: Add missing SPI support |
Date: |
Thu, 31 Dec 2020 19:29:48 +0800 |
From: Bin Meng <bin.meng@windriver.com>
This adds the missing SPI support to the `sifive_u` machine in the QEMU
mainline. With this series, upstream U-Boot for the SiFive HiFive Unleashed
board can boot on QEMU `sifive_u` out of the box. This allows users to
develop and test the recommended RISC-V boot flow with a real world use
case: ZSBL (in QEMU) loads U-Boot SPL from SD card or SPI flash to L2LIM,
then U-Boot SPL loads the payload from SD card or SPI flash that is a
combination of OpenSBI fw_dynamic firmware and U-Boot proper.
The m25p80 model is updated to support ISSI flash series. A bunch of
ssi-sd issues are fixed, and writing to SD card in SPI mode is supported.
reST documentation for RISC-V is added. Currently only `sifive_u`
machine is documented, but more to come.
Bin Meng (22):
hw/block: m25p80: Add ISSI SPI flash support
hw/block: m25p80: Add various ISSI flash information
hw/sd: ssi-sd: Fix incorrect card response sequence
hw/sd: sd: Support CMD59 for SPI mode
hw/sd: sd: Drop sd_crc16()
util: Add CRC16 (CCITT) calculation routines
hw/sd: ssi-sd: Suffix a data block with CRC16
hw/sd: ssi-sd: Support multiple block read (CMD18)
hw/sd: ssi-sd: Use macros for the dummy value and tokens in the
transfer
hw/sd: sd: Remove duplicated codes in single/multiple block read/write
hw/sd: sd: Allow single/multiple block write for SPI mode
hw/sd: sd.h: Cosmetic change of using spaces
hw/sd: Introduce receive_ready() callback
hw/sd: ssi-sd: Support single block write
hw/sd: ssi-sd: Support multiple block write
hw/ssi: Add SiFive SPI controller support
hw/riscv: sifive_u: Add QSPI0 controller and connect a flash
hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card
hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value
docs/system: Sort targets in alphabetical order
docs/system: Add RISC-V documentation
docs/system: riscv: Add documentation for sifive_u machine
docs/system/riscv/sifive_u.rst | 336 +++++++++++++++++++++++++++++++++
docs/system/target-riscv.rst | 72 +++++++
docs/system/targets.rst | 20 +-
include/hw/riscv/sifive_u.h | 9 +-
include/hw/sd/sd.h | 44 ++---
include/hw/ssi/sifive_spi.h | 47 +++++
include/qemu/crc-ccitt.h | 33 ++++
hw/block/m25p80.c | 51 ++++-
hw/riscv/sifive_u.c | 91 +++++++++
hw/sd/core.c | 13 ++
hw/sd/sd.c | 82 +-------
hw/sd/ssi-sd.c | 127 +++++++++++--
hw/ssi/sifive_spi.c | 290 ++++++++++++++++++++++++++++
util/crc-ccitt.c | 127 +++++++++++++
hw/riscv/Kconfig | 3 +
hw/ssi/Kconfig | 4 +
hw/ssi/meson.build | 1 +
util/meson.build | 1 +
18 files changed, 1232 insertions(+), 119 deletions(-)
create mode 100644 docs/system/riscv/sifive_u.rst
create mode 100644 docs/system/target-riscv.rst
create mode 100644 include/hw/ssi/sifive_spi.h
create mode 100644 include/qemu/crc-ccitt.h
create mode 100644 hw/ssi/sifive_spi.c
create mode 100644 util/crc-ccitt.c
--
2.25.1
- [PATCH 00/22] hw/riscv: sifive_u: Add missing SPI support,
Bin Meng <=
- [PATCH 01/22] hw/block: m25p80: Add ISSI SPI flash support, Bin Meng, 2020/12/31
- [PATCH 02/22] hw/block: m25p80: Add various ISSI flash information, Bin Meng, 2020/12/31
- [PATCH 03/22] hw/sd: ssi-sd: Fix incorrect card response sequence, Bin Meng, 2020/12/31
- [PATCH 04/22] hw/sd: sd: Support CMD59 for SPI mode, Bin Meng, 2020/12/31
- [PATCH 05/22] hw/sd: sd: Drop sd_crc16(), Bin Meng, 2020/12/31
- [PATCH 06/22] util: Add CRC16 (CCITT) calculation routines, Bin Meng, 2020/12/31
- [PATCH 07/22] hw/sd: ssi-sd: Suffix a data block with CRC16, Bin Meng, 2020/12/31
- [PATCH 08/22] hw/sd: ssi-sd: Support multiple block read (CMD18), Bin Meng, 2020/12/31
- [PATCH 09/22] hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer, Bin Meng, 2020/12/31
- [PATCH 11/22] hw/sd: sd: Allow single/multiple block write for SPI mode, Bin Meng, 2020/12/31