Re: [PATCH v3 0/8] support AST2700 network

[Cédric Le Goater]

On 7/4/24 10:29 AM, Jamin Lin wrote:
> change from v1:
> - ftgmac100
>   - fix coding style
>   - support 64 bits dma dram address for AST2700
>
> change from v2:
> - ftgmac100: update memory region size to 0x200.
> - ftgmac100: introduce a new class(ftgmac100_high),
>      class attribute and memop handlers, for FTGMAC100_*_HIGH regs read/write.
> - aspeed_ast27x0: update network model to ftgmac100_high to support
>    64 bits dram address DMA.
> - m25p80: support quad mode for w25q01jvq
>
> change from v3:
> - ftgmac100: update memory region size to 64KB.
> - ftgmac100: using a property to activate the region for new registers,
>    instead of a class
> - ftgmac100: introduce TX and RX ring base address high registers
> - ftgmac100: split standalone patch for easy review
> - ftgmac100: update TX and RX packet buffers address to 64 bits
> - aspeed_ast27x0: set dma64 property for AST2700 ftgmac100
> - machine_aspeed.py: update to test sdk v09.02 and network for AST2700
>
> Jamin Lin (8):
>    hw/net:ftgmac100: update memory region size to 64KB
>    hw/net:ftgmac100: update ring base address to 64 bits
>    hw/net:ftgmac100: introduce TX and RX ring base address high registers
>      to support 64 bits
>    hw/net:ftgmac100: update TX and RX packet buffers address to 64 bits
>    aspeed/soc: set dma64 property for AST2700 ftgmac100
>    hw/block: m25p80: support quad mode for w25q01jvq
>    machine_aspeed.py: update to test ASPEED OpenBMC SDK v09.02 for
>      AST2700
>    machine_aspeed.py: update to test network for AST2700
>
>   hw/arm/aspeed_ast27x0.c         |   3 +
>   hw/block/m25p80.c               |  16 ++++
>   hw/net/ftgmac100.c              | 147 +++++++++++++++++++++++++++-----
>   include/hw/net/ftgmac100.h      |  17 ++--
>   tests/avocado/machine_aspeed.py |  12 +--
>   5 files changed, 162 insertions(+), 33 deletions(-)


Applied to aspeed-next.

Thanks,

C.