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[Qemu-commits] [qemu/qemu] f7767c: target/arm: Disable SME if SVE is dis
|
From: |
Alex Bennée |
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Subject: |
[Qemu-commits] [qemu/qemu] f7767c: target/arm: Disable SME if SVE is disabled |
|
Date: |
Mon, 04 Dec 2023 10:52:19 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: f7767ca301796334f74b9b642b395a4bd3e3dbac
https://github.com/qemu/qemu/commit/f7767ca301796334f74b9b642b395a4bd3e3dbac
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-12-04 (Mon, 04 Dec 2023)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Disable SME if SVE is disabled
There is no architectural requirement that SME implies SVE, but
our implementation currently assumes it. (FEAT_SME_FA64 does
imply SVE.) So if you try to run a CPU with eg "-cpu max,sve=off"
you quickly run into an assert when the guest tries to write to
SMCR_EL1:
#6 0x00007ffff4b38e96 in __GI___assert_fail
(assertion=0x5555566e69cb "sm", file=0x5555566e5b24
"../../target/arm/helper.c", line=6865, function=0x5555566e82f0
<__PRETTY_FUNCTION__.31> "sve_vqm1_for_el_sm") at ./assert/assert.c:101
#7 0x0000555555ee33aa in sve_vqm1_for_el_sm (env=0x555557d291f0, el=2,
sm=false) at ../../target/arm/helper.c:6865
#8 0x0000555555ee3407 in sve_vqm1_for_el (env=0x555557d291f0, el=2) at
../../target/arm/helper.c:6871
#9 0x0000555555ee3724 in smcr_write (env=0x555557d291f0, ri=0x555557da23b0,
value=2147483663) at ../../target/arm/helper.c:6995
#10 0x0000555555fd1dba in helper_set_cp_reg64 (env=0x555557d291f0,
rip=0x555557da23b0, value=2147483663) at ../../target/arm/tcg/op_helper.c:839
#11 0x00007fff60056781 in code_gen_buffer ()
Avoid this unsupported and slightly odd combination by
disabling SME when SVE is not present.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2005
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231127173318.674758-1-peter.maydell@linaro.org
Commit: 5689d4bda6aa64163cf64d6b26f9de28aabed97a
https://github.com/qemu/qemu/commit/5689d4bda6aa64163cf64d6b26f9de28aabed97a
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-12-04 (Mon, 04 Dec 2023)
Changed paths:
M tests/qemu-iotests/149
M tests/qemu-iotests/149.out
Log Message:
-----------
tests/qemu-iotests/149: Use more inclusive language in this test
Let's use 'unsupported_configs' and 'tested_configs' here
instead of non-inclusive words.
Message-ID: <20231122084000.809696-1-thuth@redhat.com>
Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 55339361276a81ab3d306e6e8e81151e2977c5da
https://github.com/qemu/qemu/commit/55339361276a81ab3d306e6e8e81151e2977c5da
Author: Yihuan Pan <xun794@gmail.com>
Date: 2023-12-04 (Mon, 04 Dec 2023)
Changed paths:
M linux-user/sh4/termbits.h
M target/sh4/cpu.h
M target/sh4/helper.c
M target/sh4/op_helper.c
M target/sh4/translate.c
Log Message:
-----------
sh4: Coding style: Remove tabs
Replaces TABS with spaces to ensure have a consistent coding
style with an indentation of 4 spaces in the SH4 subsystem.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/376
Signed-off-by: Yihuan Pan <xun794@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231124044554.513752-1-xun794@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 4d98618b8a657f1ce361d90e0eade759af912b98
https://github.com/qemu/qemu/commit/4d98618b8a657f1ce361d90e0eade759af912b98
Author: Zhu Jun <zhujun2@cmss.chinamobile.com>
Date: 2023-12-04 (Mon, 04 Dec 2023)
Changed paths:
M tests/qtest/test-filter-mirror.c
M tests/qtest/test-filter-redirector.c
M tests/qtest/virtio-net-test.c
Log Message:
-----------
tests/qtest: check the return value
These variables "ret" are never referenced in the code, thus
add check logic for the "ret"
Signed-off-by: Zhu Jun <zhujun2@cmss.chinamobile.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231121080802.4500-1-zhujun2@cmss.chinamobile.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 2b8fe81b3c2e76d241510a9a85496d544e42f5ec
https://github.com/qemu/qemu/commit/2b8fe81b3c2e76d241510a9a85496d544e42f5ec
Author: Patrick Venture <venture@google.com>
Date: 2023-12-04 (Mon, 04 Dec 2023)
Changed paths:
M system/memory.c
Log Message:
-----------
system/memory: use ldn_he_p/stn_he_p
Using direct pointer dereferencing can allow for unaligned accesses,
which was seen during execution with sanitizers enabled.
Cc: qemu-stable@nongnu.org
Reviewed-by: Chris Rauer <crauer@google.com>
Reviewed-by: Peter Foley <pefoley@google.com>
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-ID: <20231116163633.276671-1-venture@google.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 560b8e1d7071e20ec14af2cc0b7096db50a0ca5c
https://github.com/qemu/qemu/commit/560b8e1d7071e20ec14af2cc0b7096db50a0ca5c
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-12-04 (Mon, 04 Dec 2023)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: fix shadowing in kvm_riscv_(get|put)_regs_csr
KVM_RISCV_GET_CSR() and KVM_RISCV_SET_CSR() use an 'int ret' variable
that is used to do an early 'return' if ret > 0. Both are being called
in functions that are also declaring a 'ret' integer, initialized with
'0', and this integer is used as return of the function.
The result is that the compiler is less than pleased and is pointing
shadowing errors:
../target/riscv/kvm/kvm-cpu.c: In function 'kvm_riscv_get_regs_csr':
../target/riscv/kvm/kvm-cpu.c:90:13: error: declaration of 'ret' shadows a
previous local [-Werror=shadow=compatible-local]
90 | int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
| ^~~
../target/riscv/kvm/kvm-cpu.c:539:5: note: in expansion of macro
'KVM_RISCV_GET_CSR'
539 | KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus);
| ^~~~~~~~~~~~~~~~~
../target/riscv/kvm/kvm-cpu.c:536:9: note: shadowed declaration is here
536 | int ret = 0;
| ^~~
../target/riscv/kvm/kvm-cpu.c: In function 'kvm_riscv_put_regs_csr':
../target/riscv/kvm/kvm-cpu.c:98:13: error: declaration of 'ret' shadows a
previous local [-Werror=shadow=compatible-local]
98 | int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
| ^~~
../target/riscv/kvm/kvm-cpu.c:556:5: note: in expansion of macro
'KVM_RISCV_SET_CSR'
556 | KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus);
| ^~~~~~~~~~~~~~~~~
../target/riscv/kvm/kvm-cpu.c:553:9: note: shadowed declaration is here
553 | int ret = 0;
| ^~~
The macros are doing early returns for non-zero returns and the local
'ret' variable for both functions is used just to do 'return 0', so
remove them from kvm_riscv_get_regs_csr() and kvm_riscv_put_regs_csr()
and do a straight 'return 0' in the end.
For good measure let's also rename the 'ret' variables in
KVM_RISCV_GET_CSR() and KVM_RISCV_SET_CSR() to '_ret' to make them more
resilient to these kind of errors.
Fixes: 937f0b4512 ("target/riscv: Implement kvm_arch_get_registers")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231123101338.1040134-1-dbarboza@ventanamicro.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: d369ad55587330ebc7bd7be463ba27884f449606
https://github.com/qemu/qemu/commit/d369ad55587330ebc7bd7be463ba27884f449606
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-12-04 (Mon, 04 Dec 2023)
Changed paths:
M tests/avocado/machine_mips_malta.py
Log Message:
-----------
tests/avocado: Update yamon-bin-02.22.zip URL
http://www.imgtec.com/tools/mips-tools/downloads/ redirects
to https://mips.com/downloads/yamon-version-02-22/ then points
to an invalid path to a s3 bucket. Use the correct path. The
site will eventually be fixed.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20231201205630.10837-1-philmd@linaro.org>
Commit: 2e8ed6a970e1842528f34aeb36b387834205c53a
https://github.com/qemu/qemu/commit/2e8ed6a970e1842528f34aeb36b387834205c53a
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2023-12-04 (Mon, 04 Dec 2023)
Changed paths:
M tests/avocado/replay_kernel.py
Log Message:
-----------
tests/avocado: mark ReplayKernelNormal.test_mips64el_malta as flaky
I missed this when going through the recent failure logs. I can run
the test 30 times without failure locally but it seems to hang pretty
reliably on GitLab's CI infra-structure.
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231201201027.2689404-1-alex.bennee@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 169c4e77640b6ab6d7665ed0839873c1bc8d766d
https://github.com/qemu/qemu/commit/169c4e77640b6ab6d7665ed0839873c1bc8d766d
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-12-04 (Mon, 04 Dec 2023)
Changed paths:
M linux-user/sh4/termbits.h
M target/sh4/cpu.h
M target/sh4/helper.c
M target/sh4/op_helper.c
M target/sh4/translate.c
M tests/qemu-iotests/149
M tests/qemu-iotests/149.out
M tests/qtest/test-filter-mirror.c
M tests/qtest/test-filter-redirector.c
M tests/qtest/virtio-net-test.c
Log Message:
-----------
Merge tag 'pull-request-2023-12-04' of https://gitlab.com/thuth/qemu into
staging
* Fix wording in iotest 149
* Fix whitespace issues in sh4 code (ignore checkpatch.pl warnings here)
* Make sure to check return values in qtests
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# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 04 Dec 2023 09:23:56 EST
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2023-12-04' of https://gitlab.com/thuth/qemu:
tests/qtest: check the return value
sh4: Coding style: Remove tabs
tests/qemu-iotests/149: Use more inclusive language in this test
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: db5e49e76c64d513f9162ec91a6f91217af2b1d9
https://github.com/qemu/qemu/commit/db5e49e76c64d513f9162ec91a6f91217af2b1d9
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-12-04 (Mon, 04 Dec 2023)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
Merge tag 'pull-target-arm-20231204-1' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Turn off SME if SVE is turned off (this combination doesn't
currently work and QEMU will assert if you try it)
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# gpg: Signature made Mon 04 Dec 2023 09:15:32 EST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20231204-1' of
https://git.linaro.org/people/pmaydell/qemu-arm:
target/arm: Disable SME if SVE is disabled
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: eeaaf96f553d11b3a460e3b3326f52bac767b612
https://github.com/qemu/qemu/commit/eeaaf96f553d11b3a460e3b3326f52bac767b612
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-12-04 (Mon, 04 Dec 2023)
Changed paths:
M system/memory.c
M target/riscv/kvm/kvm-cpu.c
M tests/avocado/replay_kernel.py
Log Message:
-----------
Merge tag 'misc-fixes-20231204' of https://github.com/philmd/qemu into staging
Misc fixes for 8.2
- memory: Avoid unaligned accesses (Patrick)
- target/riscv: Fix variable shadowing (Daniel)
- tests/avocado: Update URL, skip flaky test (Alex, Phil)
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# gpg: Signature made Mon 04 Dec 2023 10:23:58 EST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'misc-fixes-20231204' of https://github.com/philmd/qemu:
tests/avocado: mark ReplayKernelNormal.test_mips64el_malta as flaky
tests/avocado: Update yamon-bin-02.22.zip URL
target/riscv/kvm: fix shadowing in kvm_riscv_(get|put)_regs_csr
system/memory: use ldn_he_p/stn_he_p
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/1664d74c5073...eeaaf96f553d
- [Qemu-commits] [qemu/qemu] f7767c: target/arm: Disable SME if SVE is disabled,
Alex Bennée <=