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[Qemu-devel] [PATCH 10/16] target-arm: A64: Implement FCVTN
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 10/16] target-arm: A64: Implement FCVTN |
Date: |
Sun, 9 Mar 2014 15:11:01 +0000 |
Implement FCVTN (narrowing fp-to-fp conversions) from the SIMD
2-reg-misc category.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate-a64.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index d0df8d2..a958aa6 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -8450,13 +8450,30 @@ static void handle_2misc_narrow(DisasContext *s, int
opcode, bool u, bool is_q,
genenvfn = fns[size][u];
break;
}
+ case 0x16: /* FCVTN, FCVTN2 */
+ /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
+ if (size == 3) {
+ gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env);
+ } else {
+ TCGv_i32 tcg_lo = tcg_temp_new_i32();
+ TCGv_i32 tcg_hi = tcg_temp_new_i32();
+ tcg_gen_trunc_i64_i32(tcg_lo, tcg_op);
+ gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, cpu_env);
+ tcg_gen_shri_i64(tcg_op, tcg_op, 32);
+ tcg_gen_trunc_i64_i32(tcg_hi, tcg_op);
+ gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, cpu_env);
+ tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16);
+ tcg_temp_free_i32(tcg_lo);
+ tcg_temp_free_i32(tcg_hi);
+ }
+ break;
default:
g_assert_not_reached();
}
if (genfn) {
genfn(tcg_res[pass], tcg_op);
- } else {
+ } else if (genenvfn) {
genenvfn(tcg_res[pass], cpu_env, tcg_op);
}
@@ -8807,6 +8824,8 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
}
break;
case 0x16: /* FCVTN, FCVTN2 */
+ handle_2misc_narrow(s, opcode, 0, is_q, size, rn, rd);
+ return;
case 0x17: /* FCVTL, FCVTL2 */
case 0x18: /* FRINTN */
case 0x19: /* FRINTM */
--
1.9.0
- [Qemu-devel] [PATCH 00/16] A64 Neon patches: sixth set, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 12/16] target-arm: A64: List unsupported shift-imm opcodes, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 10/16] target-arm: A64: Implement FCVTN,
Peter Maydell <=
- [Qemu-devel] [PATCH 11/16] target-arm: A64: Implement FCVTL, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 02/16] target-arm: A64: Fix bug in add_sub_ext handling of rn, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 04/16] target-arm: A64: Add FSQRT to C3.6.17 (two misc), Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 07/16] target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 08/16] target-arm: A64: Implement SHLL, SHLL2, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 09/16] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 13/16] target-arm: A64: Add FRECPX (reciprocal exponent), Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 05/16] target-arm: A64: Add remaining CLS/Z vector ops, Peter Maydell, 2014/03/09