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Re: [Qemu-devel] [PATCH 02/16] target-arm: A64: Fix bug in add_sub_ext h
From: |
Laurent Desnogues |
Subject: |
Re: [Qemu-devel] [PATCH 02/16] target-arm: A64: Fix bug in add_sub_ext handling of rn |
Date: |
Thu, 13 Mar 2014 09:04:25 +0100 |
On Sun, Mar 9, 2014 at 4:10 PM, Peter Maydell <address@hidden> wrote:
> From: Alex Bennée <address@hidden>
>
> rn == 31 always means SP (not XZR) whether an add_sub_ext
> instruction is setting the flags or not; only rd has behaviour
> dependent on whether we are setting flags.
>
> Reported-by: Laurent Desnogues <address@hidden>
> Signed-off-by: Alex Bennée <address@hidden>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Thanks,
Laurent
> ---
> target-arm/translate-a64.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> index f89b0a5..90936cd 100644
> --- a/target-arm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -3096,12 +3096,11 @@ static void disas_add_sub_ext_reg(DisasContext *s,
> uint32_t insn)
>
> /* non-flag setting ops may use SP */
> if (!setflags) {
> - tcg_rn = read_cpu_reg_sp(s, rn, sf);
> tcg_rd = cpu_reg_sp(s, rd);
> } else {
> - tcg_rn = read_cpu_reg(s, rn, sf);
> tcg_rd = cpu_reg(s, rd);
> }
> + tcg_rn = read_cpu_reg_sp(s, rn, sf);
>
> tcg_rm = read_cpu_reg(s, rm, sf);
> ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3);
> --
> 1.9.0
>
- [Qemu-devel] [PATCH 00/16] A64 Neon patches: sixth set, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 12/16] target-arm: A64: List unsupported shift-imm opcodes, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 10/16] target-arm: A64: Implement FCVTN, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 11/16] target-arm: A64: Implement FCVTL, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 02/16] target-arm: A64: Fix bug in add_sub_ext handling of rn, Peter Maydell, 2014/03/09
- Re: [Qemu-devel] [PATCH 02/16] target-arm: A64: Fix bug in add_sub_ext handling of rn,
Laurent Desnogues <=
- [Qemu-devel] [PATCH 04/16] target-arm: A64: Add FSQRT to C3.6.17 (two misc), Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 07/16] target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 08/16] target-arm: A64: Implement SHLL, SHLL2, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 09/16] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 13/16] target-arm: A64: Add FRECPX (reciprocal exponent), Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 05/16] target-arm: A64: Add remaining CLS/Z vector ops, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 03/16] target-arm: A64: Add last AdvSIMD Integer to FP ops, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 15/16] target-arm: A64: Implement FRINT*, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 01/16] target-arm: A64: Implement PMULL instruction, Peter Maydell, 2014/03/09