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[Qemu-devel] [PATCH 20/26] tcg-aarch64: Introduce tcg_out_insn_3507
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 20/26] tcg-aarch64: Introduce tcg_out_insn_3507 |
Date: |
Fri, 14 Mar 2014 19:48:46 -0700 |
Cleaning up the implementation of REV and REV16 at the same time.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/aarch64/tcg-target.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index fa1a45d..bf4b654 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -327,6 +327,10 @@ typedef enum {
I3506_CSEL = 0x1a800000,
I3506_CSINC = 0x1a800400,
+ /* Data-processing (1 source) instructions. */
+ I3507_REV16 = 0x5ac00400,
+ I3507_REV = 0x5ac00800,
+
/* Data-processing (2 source) instructions. */
I3508_LSLV = 0x1ac02000,
I3508_LSRV = 0x1ac02400,
@@ -545,6 +549,12 @@ static void tcg_out_insn_3506(TCGContext *s, AArch64Insn
insn, TCGType ext,
| tcg_cond_to_aarch64[c] << 12);
}
+static void tcg_out_insn_3507(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn)
+{
+ tcg_out32(s, insn | ext << 31 | rn << 5 | rd);
+}
+
static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext,
TCGReg rd, TCGReg rn, TCGReg rm, TCGReg ra)
{
@@ -952,19 +962,15 @@ static void tcg_out_brcond(TCGContext *s, TCGMemOp ext,
TCGCond c, TCGArg a,
}
static inline void tcg_out_rev(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg rm)
+ TCGReg rd, TCGReg rn)
{
- /* using REV 0x5ac00800 */
- unsigned int base = ext ? 0xdac00c00 : 0x5ac00800;
- tcg_out32(s, base | rm << 5 | rd);
+ tcg_out_insn(s, 3507, REV, ext, rd, rn);
}
static inline void tcg_out_rev16(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg rm)
+ TCGReg rd, TCGReg rn)
{
- /* using REV16 0x5ac00400 */
- unsigned int base = ext ? 0xdac00400 : 0x5ac00400;
- tcg_out32(s, base | rm << 5 | rd);
+ tcg_out_insn(s, 3507, REV16, ext, rd, rn);
}
static inline void tcg_out_sxt(TCGContext *s, TCGType ext, TCGMemOp s_bits,
--
1.8.5.3
- [Qemu-devel] [PATCH 15/26] tcg-aarch64: Avoid add with zero in tlb load, (continued)
- [Qemu-devel] [PATCH 15/26] tcg-aarch64: Avoid add with zero in tlb load, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 16/26] tcg-aarch64: Use tcg_out_call for qemu_ld/st, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 17/26] tcg-aarch64: Use ADR to pass the return address to the ld/st helpers, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 18/26] tcg-aarch64: Use TCGMemOp in qemu_ld/st, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 19/26] tcg-aarch64: Implement TCG_TARGET_HAS_new_ldst, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 20/26] tcg-aarch64: Introduce tcg_out_insn_3507,
Richard Henderson <=
- [Qemu-devel] [PATCH 21/26] tcg-aarch64: Merge aarch64_ldst_get_data/type into tcg_out_op, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 22/26] tcg-aarch64: Replace aarch64_ldst_op_data with TCGMemOp, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 23/26] tcg-aarch64: Replace aarch64_ldst_op_data with AArch64LdstType, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 24/26] tcg-aarch64: Prefer unsigned offsets before signed offsets for ldst, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 25/26] tcg-aarch64: Merge tcg_out_movr with tcg_out_mov, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 26/26] tcg-aarch64: Support stores of zero, Richard Henderson, 2014/03/14