[Qemu-devel] [PATCH 25/26] tcg-aarch64: Merge tcg_out_movr with tcg_out_mov

[Richard Henderson]

In the one case we rely on zero-extension, use ORR directly.

Signed-off-by: Richard Henderson <address@hidden>
---
 tcg/aarch64/tcg-target.c | 26 +++++++++-----------------
 1 file changed, 9 insertions(+), 17 deletions(-)

diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 3bbd24c..0735ffe 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -499,12 +499,6 @@ static void tcg_out_ldst_12(TCGContext *s, TCGMemOp size, 
AArch64LdstType type,
               | scaled_uimm << 10 | rn << 5 | rd);
 }
 
-/* Register to register move using ORR (shifted register with no shift). */
-static void tcg_out_movr(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rm)
-{
-    tcg_out_insn(s, 3510, ORR, ext, rd, TCG_REG_XZR, rm);
-}
-
 /* This function is used for the Logical (immediate) instruction group.
    The value of LIMM must satisfy IS_LIMM.  See the comment above about
    only supporting simplified logical immediates.  */
@@ -660,7 +654,7 @@ static inline void tcg_out_mov(TCGContext *s,
                                TCGType type, TCGReg ret, TCGReg arg)
 {
     if (ret != arg) {
-        tcg_out_movr(s, type, ret, arg);
+        tcg_out_insn(s, 3510, ORR, type, ret, TCG_REG_XZR, arg);
     }
 }
 
@@ -942,9 +936,7 @@ static inline void tcg_out_addsub2(TCGContext *s, int ext, 
TCGReg rl,
     }
     tcg_out_insn_3503(s, insn, ext, rh, ah, bh);
 
-    if (rl != orig_rl) {
-        tcg_out_movr(s, ext, orig_rl, rl);
-    }
+    tcg_out_mov(s, ext, orig_rl, rl);
 }
 
 #ifdef CONFIG_SOFTMMU
@@ -988,15 +980,15 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, 
TCGLabelQemuLdst *lb)
 
     reloc_pc19(lb->label_ptr[0], (intptr_t)s->code_ptr);
 
-    tcg_out_movr(s, TCG_TYPE_I64, TCG_REG_X0, TCG_AREG0);
-    tcg_out_movr(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
+    tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_X0, TCG_AREG0);
+    tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
     tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, lb->mem_index);
     tcg_out_adr(s, TCG_REG_X3, (intptr_t)lb->raddr);
     tcg_out_call(s, (intptr_t)qemu_ld_helpers[opc & ~MO_SIGN]);
     if (opc & MO_SIGN) {
         tcg_out_sxt(s, TCG_TYPE_I64, size, lb->datalo_reg, TCG_REG_X0);
     } else {
-        tcg_out_movr(s, TCG_TYPE_I64, lb->datalo_reg, TCG_REG_X0);
+        tcg_out_mov(s, size == MO_64, lb->datalo_reg, TCG_REG_X0);
     }
 
     tcg_out_goto(s, (intptr_t)lb->raddr);
@@ -1009,9 +1001,9 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, 
TCGLabelQemuLdst *lb)
 
     reloc_pc19(lb->label_ptr[0], (intptr_t)s->code_ptr);
 
-    tcg_out_movr(s, TCG_TYPE_I64, TCG_REG_X0, TCG_AREG0);
-    tcg_out_movr(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
-    tcg_out_movr(s, size == MO_64, TCG_REG_X2, lb->datalo_reg);
+    tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_X0, TCG_AREG0);
+    tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
+    tcg_out_mov(s, size == MO_64, TCG_REG_X2, lb->datalo_reg);
     tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, lb->mem_index);
     tcg_out_adr(s, TCG_REG_X4, (intptr_t)lb->raddr);
     tcg_out_call(s, (intptr_t)qemu_st_helpers[opc]);
@@ -1568,7 +1560,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_out_uxt(s, MO_16, a0, a1);
         break;
     case INDEX_op_ext32u_i64:
-        tcg_out_movr(s, TCG_TYPE_I32, a0, a1);
+        tcg_out_insn(s, 3510, ORR, TCG_TYPE_I32, a0, TCG_REG_XZR, a1);
         break;
 
     case INDEX_op_deposit_i64:
-- 
1.8.5.3