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[Qemu-devel] [PATCH v5 35/37] target-arm: Make Cortex-A15 CBAR read-only
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v5 35/37] target-arm: Make Cortex-A15 CBAR read-only |
Date: |
Fri, 28 Mar 2014 16:10:22 +0000 |
The Cortex-A15's CBAR register is actually read-only (unlike that
of the Cortex-A9). Correct our model to match the hardware.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index f9f6187..c0ddc3e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -744,7 +744,7 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
- set_feature(&cpu->env, ARM_FEATURE_CBAR);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
set_feature(&cpu->env, ARM_FEATURE_LPAE);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
cpu->midr = 0x412fc0f1;
--
1.9.0
- [Qemu-devel] [PATCH v5 00/37] AArch64 system emulation, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 22/37] hw/arm/virt: Add support for Cortex-A57, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 34/37] target-arm: Implement CBAR for Cortex-A57, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 16/37] target-arm: Implement SP_EL0, SP_EL1, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 10/37] target-arm: Add v8 mmu translation support, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 32/37] target-arm: Implement RVBAR register, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 25/37] target-arm: Implement AArch64 view of ACTLR, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 24/37] target-arm: Implement AArch64 view of CONTEXTIDR, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 01/37] target-arm: Split out private-to-target functions into internals.h, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 15/37] target-arm: Add AArch64 ELR_EL1 register., Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 35/37] target-arm: Make Cortex-A15 CBAR read-only,
Peter Maydell <=
- [Qemu-devel] [PATCH v5 04/37] target-arm: Provide correct syndrome information for cpreg access traps, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 03/37] target-arm: Define exception record for AArch64 exceptions, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 28/37] target-arm: Don't expose wildcard ID register definitions for ARMv8, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 07/37] target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 37/37] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 29/37] target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 31/37] target-arm: Implement AArch64 address translation operations, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 33/37] target-arm: Implement Cortex-A57 implementation-defined system registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 14/37] target-arm: Implement AArch64 views of fault status and data registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 11/37] target-arm: Don't mention PMU in debug feature register, Peter Maydell, 2014/03/28