[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 08/11] target-arm: A64: Avoid duplicate exit_tb(0) i
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 08/11] target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb |
Date: |
Fri, 8 Aug 2014 13:18:11 +0100 |
If gen_goto_tb() decides not to link the two TBs, then the
fallback path generates unnecessary code:
* if singlestep is enabled then we generate unreachable code
after the gen_exception_internal(EXCP_DEBUG)
* if singlestep is disabled then we will generate exit_tb(0)
twice, once in gen_goto_tb() and once coming out of the
main loop with is_jmp set to DISAS_JUMP
Correct these deficiencies by only emitting exit_tb() in the
non-singlestep case, in which case we can use DISAS_TB_JUMP
to suppress the main-loop exit_tb().
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate-a64.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 33b5025..aa731bf 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -232,9 +232,10 @@ static inline void gen_goto_tb(DisasContext *s, int n,
uint64_t dest)
gen_a64_set_pc_im(dest);
if (s->singlestep_enabled) {
gen_exception_internal(EXCP_DEBUG);
+ } else {
+ tcg_gen_exit_tb(0);
+ s->is_jmp = DISAS_TB_JUMP;
}
- tcg_gen_exit_tb(0);
- s->is_jmp = DISAS_JUMP;
}
}
--
1.9.1
- [Qemu-devel] [PATCH 00/11] target-arm: Implement ARMv8 debug single-stepping, Peter Maydell, 2014/08/08
- [Qemu-devel] [PATCH 05/11] target-arm: Don't allow AArch32 to access RES0 CPSR bits, Peter Maydell, 2014/08/08
- [Qemu-devel] [PATCH 08/11] target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb,
Peter Maydell <=
- [Qemu-devel] [PATCH 07/11] target-arm: Set PSTATE.SS correctly on exception return from AArch64, Peter Maydell, 2014/08/08
- [Qemu-devel] [PATCH 06/11] target-arm: Correctly handle PSTATE.SS when taking exception to AArch32, Peter Maydell, 2014/08/08
- [Qemu-devel] [PATCH 04/11] target-arm: Adjust debug ID registers per-CPU, Peter Maydell, 2014/08/08
- [Qemu-devel] [PATCH 03/11] target-arm: Provide both 32 and 64 bit versions of debug registers, Peter Maydell, 2014/08/08
- [Qemu-devel] [PATCH 01/11] target-arm: Collect up the debug cp register definitions, Peter Maydell, 2014/08/08
- [Qemu-devel] [PATCH 09/11] target-arm: Implement ARMv8 single-step handling for A64 code, Peter Maydell, 2014/08/08