[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 09/11] target-arm: Implement ARMv8 single-step h
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 09/11] target-arm: Implement ARMv8 single-step handling for A64 code |
Date: |
Tue, 19 Aug 2014 11:46:23 +0100 |
On 19 August 2014 11:25, Peter Maydell <address@hidden> wrote:
> On 19 August 2014 10:56, Edgar E. Iglesias <address@hidden> wrote:
>> On Fri, Aug 08, 2014 at 01:18:12PM +0100, Peter Maydell wrote:
>>> --- a/target-arm/cpu.h
>>> +++ b/target-arm/cpu.h
>>> @@ -1211,6 +1211,10 @@ static inline bool arm_singlestep_active(CPUARMState
>>> *env)
>>> #define ARM_TBFLAG_AA64_EL_MASK (0x3 << ARM_TBFLAG_AA64_EL_SHIFT)
>>> #define ARM_TBFLAG_AA64_FPEN_SHIFT 2
>>> #define ARM_TBFLAG_AA64_FPEN_MASK (1 << ARM_TBFLAG_AA64_FPEN_SHIFT)
>>> +#define ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT 3
>>> +#define ARM_TBFLAG_AA64_SS_ACTIVE_MASK (1 <<
>>> ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT)
>>> +#define ARM_TBFLAG_AA64_PSTATE_SS_SHIFT 3
>>> +#define ARM_TBFLAG_AA64_PSTATE_SS_MASK (1 <<
>>> ARM_TBFLAG_AA64_PSTATE_SS_SHIFT)
>>
>> Shouldn't these shifts/masks differ?
>
> Oops. Yes, they certainly should.
The fix is just a simple s/3/4/ for the PSTATE_SS_SHIFT
define. Does anybody want a retransmit of the series for
this one-liner?
thanks
-- PMM
- [Qemu-devel] [PATCH 05/11] target-arm: Don't allow AArch32 to access RES0 CPSR bits, (continued)
- [Qemu-devel] [PATCH 05/11] target-arm: Don't allow AArch32 to access RES0 CPSR bits, Peter Maydell, 2014/08/08
- [Qemu-devel] [PATCH 08/11] target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb, Peter Maydell, 2014/08/08
- [Qemu-devel] [PATCH 07/11] target-arm: Set PSTATE.SS correctly on exception return from AArch64, Peter Maydell, 2014/08/08
- [Qemu-devel] [PATCH 06/11] target-arm: Correctly handle PSTATE.SS when taking exception to AArch32, Peter Maydell, 2014/08/08
- [Qemu-devel] [PATCH 04/11] target-arm: Adjust debug ID registers per-CPU, Peter Maydell, 2014/08/08
- [Qemu-devel] [PATCH 03/11] target-arm: Provide both 32 and 64 bit versions of debug registers, Peter Maydell, 2014/08/08
- [Qemu-devel] [PATCH 01/11] target-arm: Collect up the debug cp register definitions, Peter Maydell, 2014/08/08
- [Qemu-devel] [PATCH 09/11] target-arm: Implement ARMv8 single-step handling for A64 code, Peter Maydell, 2014/08/08
[Qemu-devel] [PATCH 02/11] target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14, Peter Maydell, 2014/08/08
[Qemu-devel] [PATCH 10/11] target-arm: Implement ARMv8 single-stepping for AArch32 code, Peter Maydell, 2014/08/08
[Qemu-devel] [PATCH 11/11] target-arm: Implement MDSCR_EL1 as having state, Peter Maydell, 2014/08/08
Re: [Qemu-devel] [PATCH 00/11] target-arm: Implement ARMv8 debug single-stepping, Peter Maydell, 2014/08/18