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Re: [Qemu-devel] [PATCH 2/3] arm_gic: SGIs for GICD_ICFGR are WI
From: |
Christoffer Dall |
Subject: |
Re: [Qemu-devel] [PATCH 2/3] arm_gic: SGIs for GICD_ICFGR are WI |
Date: |
Fri, 15 Aug 2014 14:12:17 +0200 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Sun, Aug 03, 2014 at 10:53:46AM +0200, Adam Lackorzynski wrote:
> Writes to SGIs for GICD_ICFGR register must be ignored.
>
> Signed-off-by: Adam Lackorzynski <address@hidden>
> ---
> hw/intc/arm_gic.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index d2b1aaf..cd6e6ea 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -566,10 +566,13 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
> } else {
> GIC_CLEAR_MODEL(irq + i);
> }
> - if (value & (2 << (i * 2))) {
> - GIC_SET_EDGE_TRIGGER(irq + i);
> - } else {
> - GIC_CLEAR_EDGE_TRIGGER(irq + i);
> + /* SGIs are WI */
> + if (irq >= 16) {
> + if (value & (2 << (i * 2))) {
> + GIC_SET_EDGE_TRIGGER(irq + i);
> + } else {
> + GIC_CLEAR_EDGE_TRIGGER(irq + i);
> + }
> }
> }
> } else if (offset < 0xf10) {
Actually, this looks a bit weird given that you do set the model bit,
which should probably be treated as WI/RAZ for a GICv2 emulation, but
you don't set the edge trigger bit for them.
I think a cleaner fix might be to to just change the existing check from
(irq < GIC_INTERNAL) to (irq < GIT_NR_SGIS), then you also don't need
the next patch.
-Christoffer