[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v1 09/30] target-sparc: implement UltraSPARC-T1 Stra
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PATCH v1 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR |
Date: |
Fri, 4 Nov 2016 21:50:10 +0100 |
Signed-off-by: Artyom Tarasenko <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-sparc/translate.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 0b0cde1..b898898 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -3429,6 +3429,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
case 0x19: /* System tick compare */
gen_store_gpr(dc, rd, cpu_stick_cmpr);
break;
+ case 0x1a: /* UltraSPARC-T1 Strand status */
+ /* XXX HYPV check maybe not enough, UA2005 & UA2007
describe
+ * this ASR as impl. dep
+ */
+ CHECK_IU_FEATURE(dc, HYPV);
+ {
+ TCGv t = gen_dest_gpr(dc, rd);
+ tcg_gen_movi_tl(t, 1UL);
+ gen_store_gpr(dc, rd, t);
+ }
+ break;
case 0x10: /* Performance Control */
case 0x11: /* Performance Instrumentation Counter */
case 0x12: /* Dispatch Control */
--
1.8.3.1
- Re: [Qemu-devel] [PATCH v1 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode, (continued)
- [Qemu-devel] [PATCH v1 02/30] target-sparc: store cpu super- and hypervisor flags in TB, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 03/30] target-sparc: use explicit mmu register pointers, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 04/30] target-sparc: add UA2005 TTE bit #defines, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 05/30] target-sparc: add UltraSPARC T1 TLB #defines, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 08/30] target-sparc: implement UA2005 scratchpad registers, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR,
Artyom Tarasenko <=
- [Qemu-devel] [PATCH v1 10/30] target-sparc: hypervisor mode takes over nucleus mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 11/30] target-sparc: implement UA2005 hypervisor traps, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 14/30] target-sparc: fix immediate UA2005 traps, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 12/30] target-sparc: implement UA2005 GL register, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 18/30] target-sparc: replace the last tlb entry when no free entries left, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 15/30] target-sparc: use direct address translation in hyperprivileged mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs, Artyom Tarasenko, 2016/11/04