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Re: [Qemu-devel] [PATCH v1 01/30] target-sparc: ignore MMU-faults if MMU
From: |
Artyom Tarasenko |
Subject: |
Re: [Qemu-devel] [PATCH v1 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode |
Date: |
Sat, 5 Nov 2016 22:20:54 +0100 |
On Fri, Nov 4, 2016 at 10:19 PM, Richard Henderson <address@hidden> wrote:
> On 11/04/2016 02:50 PM, Artyom Tarasenko wrote:
>>
>> + if (is_exec) { /* XXX has_hypervisor */
>> + if (env->lsu & (IMMU_E)) {
>> + cpu_raise_exception_ra(env, TT_CODE_ACCESS, GETPC());
>> + } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV))
>> {
>> + cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS,
>> GETPC());
>> + }
>> + } else {
>> + if (env->lsu & (DMMU_E)) {
>> + cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC());
>> + } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV))
>> {
>> + cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS,
>> GETPC());
>> + }
>> + }
>
>
> And if the hypervisor itself has a bug and references bad memory?
The MMU is usually switched on. The exception is the early initialization.
> Or does
> the hypervisor *have* to do such things in order to probe for device on
> startup, and should therefore not trap.
>
> I'm actually assuming this is the case based on the fact that you wrote this
> patch in the first place.
Yep.
> But if so, we need a comment here.
With MMU switched off there is no circuit which would produce a MMU fault.
Neither under sun4v nor under sun4u. Do we really have to document it?
Btw it works the same way under sun4m just 26 lines above.
--
Regards,
Artyom Tarasenko
SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu
- [Qemu-devel] [PATCH v1 00/30] target-sparc: add niagara OpenSPARC T1 sun4v emulation, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 02/30] target-sparc: store cpu super- and hypervisor flags in TB, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 03/30] target-sparc: use explicit mmu register pointers, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 04/30] target-sparc: add UA2005 TTE bit #defines, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 05/30] target-sparc: add UltraSPARC T1 TLB #defines, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 08/30] target-sparc: implement UA2005 scratchpad registers, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR, Artyom Tarasenko, 2016/11/04
- [Qemu-devel] [PATCH v1 10/30] target-sparc: hypervisor mode takes over nucleus mode, Artyom Tarasenko, 2016/11/04