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[PATCH v6 24/41] target/arm: Update ctr_el0_access for EL2
From: |
Richard Henderson |
Subject: |
[PATCH v6 24/41] target/arm: Update ctr_el0_access for EL2 |
Date: |
Sat, 1 Feb 2020 11:28:59 -0800 |
Update to include checks against HCR_EL2.TID2.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 26 +++++++++++++++++++++-----
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e41bece6b5..72b336e3b5 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5264,11 +5264,27 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
- /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
- * but the AArch32 CTR has its own reginfo struct)
- */
- if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
- return CP_ACCESS_TRAP;
+ int cur_el = arm_current_el(env);
+
+ if (cur_el < 2) {
+ uint64_t hcr = arm_hcr_el2_eff(env);
+
+ if (cur_el == 0) {
+ if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
+ if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ } else {
+ if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
+ return CP_ACCESS_TRAP;
+ }
+ if (hcr & HCR_TID2) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ }
+ } else if (hcr & HCR_TID2) {
+ return CP_ACCESS_TRAP_EL2;
+ }
}
if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) {
--
2.20.1
- [PATCH v6 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2, (continued)
- [PATCH v6 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2, Richard Henderson, 2020/02/01
- [PATCH v6 15/41] target/arm: Recover 4 bits from TBFLAGs, Richard Henderson, 2020/02/01
- [PATCH v6 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions, Richard Henderson, 2020/02/01
- [PATCH v6 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits, Richard Henderson, 2020/02/01
- [PATCH v6 20/41] target/arm: Add regime_has_2_ranges, Richard Henderson, 2020/02/01
- [PATCH v6 17/41] target/arm: Rearrange ARMMMUIdxBit, Richard Henderson, 2020/02/01
- [PATCH v6 19/41] target/arm: Reorganize ARMMMUIdx, Richard Henderson, 2020/02/01
- [PATCH v6 21/41] target/arm: Update arm_mmu_idx for VHE, Richard Henderson, 2020/02/01
- [PATCH v6 22/41] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2020/02/01
- [PATCH v6 23/41] target/arm: Update aa64_zva_access for EL2, Richard Henderson, 2020/02/01
- [PATCH v6 24/41] target/arm: Update ctr_el0_access for EL2,
Richard Henderson <=
- [PATCH v6 25/41] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2020/02/01
- [PATCH v6 26/41] target/arm: Update timer access for VHE, Richard Henderson, 2020/02/01
- [PATCH v6 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, Richard Henderson, 2020/02/01
- [PATCH v6 28/41] target/arm: Add VHE system register redirection and aliasing, Richard Henderson, 2020/02/01
- [PATCH v6 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Richard Henderson, 2020/02/01
- [PATCH v6 29/41] target/arm: Add VHE timer register redirection and aliasing, Richard Henderson, 2020/02/01
- [PATCH v6 31/41] target/arm: Flush tlbs for E2&0 translation regime, Richard Henderson, 2020/02/01