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Re: [PATCH v6 30/41] target/arm: Flush tlb for ASID changes in EL2&0 tra
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v6 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime |
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Date: |
Tue, 4 Feb 2020 13:58:10 +0000 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 2/3/20 11:49 AM, Peter Maydell wrote:
> On Mon, 3 Feb 2020 at 11:36, Peter Maydell <address@hidden> wrote:
>> Since we don't flush TLBs when HCR_EL2.E2H changes, I'm wondering
>> about this sequence:
>>
>> * initially HCR_EL2.E2H == 1 and the E2&0 TLBs are populated
>> * HCR_EL2.E2H is set to 0
>> * TTBR1_EL2 is written with a different ASID from step 1,
>> but we don't flush the TLBs because HCR_EL2.E2H is 0
>> * HCR_EL2.E2H is set to 1
>> * guest will pick up wrong-ASID TLB entries from step 1
>>
>> Does the architecture require that the guest did some TLB
>> maintenance ops somewhere along the line to avoid this?
>> I haven't tried to look for them, but given the different
>> ASIDs I'm not sure it does...
>
> ...HCR_EL2.E2H documents that it "is permitted to be cached
> in a TLB", which means that the guest has to do *some*
> TLB maintenance ops if it changes it; unclear exactly which,
> though...
TLBI ALLE2 would seem to fit the bill after E2H change.
r~
- [PATCH v6 22/41] target/arm: Update arm_sctlr for VHE, (continued)
- [PATCH v6 22/41] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2020/02/01
- [PATCH v6 23/41] target/arm: Update aa64_zva_access for EL2, Richard Henderson, 2020/02/01
- [PATCH v6 24/41] target/arm: Update ctr_el0_access for EL2, Richard Henderson, 2020/02/01
- [PATCH v6 25/41] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2020/02/01
- [PATCH v6 26/41] target/arm: Update timer access for VHE, Richard Henderson, 2020/02/01
- [PATCH v6 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, Richard Henderson, 2020/02/01
- [PATCH v6 28/41] target/arm: Add VHE system register redirection and aliasing, Richard Henderson, 2020/02/01
- [PATCH v6 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Richard Henderson, 2020/02/01
- [PATCH v6 29/41] target/arm: Add VHE timer register redirection and aliasing, Richard Henderson, 2020/02/01
- [PATCH v6 31/41] target/arm: Flush tlbs for E2&0 translation regime, Richard Henderson, 2020/02/01
- [PATCH v6 32/41] target/arm: Update arm_phys_excp_target_el for TGE, Richard Henderson, 2020/02/01
- [PATCH v6 33/41] target/arm: Update {fp,sve}_exception_el for VHE, Richard Henderson, 2020/02/01
- [PATCH v6 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps, Richard Henderson, 2020/02/01
- [PATCH v6 35/41] target/arm: Update get_a64_user_mem_index for VHE, Richard Henderson, 2020/02/01
- [PATCH v6 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE, Richard Henderson, 2020/02/01
- [PATCH v6 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max, Richard Henderson, 2020/02/01
- [PATCH v6 38/41] target/arm: Move arm_excp_unmasked to cpu.c, Richard Henderson, 2020/02/01