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[PATCH v2 03/14] target/arm: Add isar_feature tests for PAN + ATS1E1
From: |
Richard Henderson |
Subject: |
[PATCH v2 03/14] target/arm: Add isar_feature tests for PAN + ATS1E1 |
Date: |
Sat, 1 Feb 2020 17:04:28 -0800 |
Include definitions for all of the bits in ID_MMFR3.
We already have a definition for ID_AA64MMFR1.PAN.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.h | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c63bceaaa5..08b2f5d73e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1727,6 +1727,15 @@ FIELD(ID_ISAR6, FHM, 8, 4)
FIELD(ID_ISAR6, SB, 12, 4)
FIELD(ID_ISAR6, SPECRES, 16, 4)
+FIELD(ID_MMFR3, CMAINTVA, 0, 4)
+FIELD(ID_MMFR3, CMAINTSW, 4, 4)
+FIELD(ID_MMFR3, BPMAINT, 8, 4)
+FIELD(ID_MMFR3, MAINTBCST, 12, 4)
+FIELD(ID_MMFR3, PAN, 16, 4)
+FIELD(ID_MMFR3, COHWALK, 20, 4)
+FIELD(ID_MMFR3, CMEMSZ, 24, 4)
+FIELD(ID_MMFR3, SUPERSEC, 28, 4)
+
FIELD(ID_MMFR4, SPECSEI, 0, 4)
FIELD(ID_MMFR4, AC2, 4, 4)
FIELD(ID_MMFR4, XNX, 8, 4)
@@ -3443,6 +3452,16 @@ static inline bool isar_feature_aa32_vminmaxnm(const
ARMISARegisters *id)
return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
}
+static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0;
+}
+
+static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2;
+}
+
/*
* 64-bit feature tests via id registers.
*/
@@ -3602,6 +3621,16 @@ static inline bool isar_feature_aa64_lor(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
}
+static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
+}
+
+static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
+}
+
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
--
2.20.1
- [PATCH v2 00/14] target/arm: Implement PAN, ATS1E1, UAO, Richard Henderson, 2020/02/01
- [PATCH v2 01/14] target/arm: Add arm_mmu_idx_is_stage1_of_2, Richard Henderson, 2020/02/01
- [PATCH v2 02/14] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled, Richard Henderson, 2020/02/01
- [PATCH v2 04/14] target/arm: Move LOR regdefs to file scope, Richard Henderson, 2020/02/01
- [PATCH v2 03/14] target/arm: Add isar_feature tests for PAN + ATS1E1,
Richard Henderson <=
- [PATCH v2 05/14] target/arm: Update MSR access for PAN, Richard Henderson, 2020/02/01
- [PATCH v2 06/14] target/arm: Update arm_mmu_idx_el for PAN, Richard Henderson, 2020/02/01
- [PATCH v2 07/14] target/arm: Enforce PAN semantics in get_S1prot, Richard Henderson, 2020/02/01
- [PATCH v2 08/14] target/arm: Set PAN bit as required on exception entry, Richard Henderson, 2020/02/01
- [PATCH v2 09/14] target/arm: Implement ATS1E1 system registers, Richard Henderson, 2020/02/01
- [PATCH v2 10/14] target/arm: Enable ARMv8.2-ATS1E1 in -cpu max, Richard Henderson, 2020/02/01