Re: [PATCH v2 04/14] target/arm: Move LOR regdefs to file scope

[Alex Bennée]

Richard Henderson <address@hidden> writes:

> For static const regdefs, file scope is preferred.
>
> Signed-off-by: Richard Henderson <address@hidden>

Reviewed-by: Alex Bennée <address@hidden>

> ---
>  target/arm/helper.c | 57 +++++++++++++++++++++++----------------------
>  1 file changed, 29 insertions(+), 28 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 739d2d4cc5..795ef727d0 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6343,6 +6343,35 @@ static CPAccessResult access_lor_other(CPUARMState 
> *env,
>      return access_lor_ns(env);
>  }
>  
> +/*
> + * A trivial implementation of ARMv8.1-LOR leaves all of these
> + * registers fixed at 0, which indicates that there are zero
> + * supported Limited Ordering regions.
> + */
> +static const ARMCPRegInfo lor_reginfo[] = {
> +    { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
> +      .access = PL1_RW, .accessfn = access_lor_other,
> +      .type = ARM_CP_CONST, .resetvalue = 0 },
> +    { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
> +      .access = PL1_RW, .accessfn = access_lor_other,
> +      .type = ARM_CP_CONST, .resetvalue = 0 },
> +    { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
> +      .access = PL1_RW, .accessfn = access_lor_other,
> +      .type = ARM_CP_CONST, .resetvalue = 0 },
> +    { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
> +      .access = PL1_RW, .accessfn = access_lor_other,
> +      .type = ARM_CP_CONST, .resetvalue = 0 },
> +    { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
> +      .access = PL1_R, .accessfn = access_lorid,
> +      .type = ARM_CP_CONST, .resetvalue = 0 },
> +    REGINFO_SENTINEL
> +};
> +
>  #ifdef TARGET_AARCH64
>  static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri,
>                                     bool isread)
> @@ -7577,34 +7606,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>      }
>  
>      if (cpu_isar_feature(aa64_lor, cpu)) {
> -        /*
> -         * A trivial implementation of ARMv8.1-LOR leaves all of these
> -         * registers fixed at 0, which indicates that there are zero
> -         * supported Limited Ordering regions.
> -         */
> -        static const ARMCPRegInfo lor_reginfo[] = {
> -            { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
> -              .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
> -              .access = PL1_RW, .accessfn = access_lor_other,
> -              .type = ARM_CP_CONST, .resetvalue = 0 },
> -            { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
> -              .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
> -              .access = PL1_RW, .accessfn = access_lor_other,
> -              .type = ARM_CP_CONST, .resetvalue = 0 },
> -            { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
> -              .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
> -              .access = PL1_RW, .accessfn = access_lor_other,
> -              .type = ARM_CP_CONST, .resetvalue = 0 },
> -            { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
> -              .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
> -              .access = PL1_RW, .accessfn = access_lor_other,
> -              .type = ARM_CP_CONST, .resetvalue = 0 },
> -            { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
> -              .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
> -              .access = PL1_R, .accessfn = access_lorid,
> -              .type = ARM_CP_CONST, .resetvalue = 0 },
> -            REGINFO_SENTINEL
> -        };
>          define_arm_cp_regs(cpu, lor_reginfo);
>      }


-- 
Alex Bennée