[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v6 31/41] target/arm: Flush tlbs for E2&0 translation regime
From: |
Peter Maydell |
Subject: |
Re: [PATCH v6 31/41] target/arm: Flush tlbs for E2&0 translation regime |
Date: |
Mon, 3 Feb 2020 11:30:12 +0000 |
On Sat, 1 Feb 2020 at 19:29, Richard Henderson
<address@hidden> wrote:
>
> Reviewed-by: Peter Maydell <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> v5: Flush all EL2 regimes with TLBI ALLE2 (pmm).
> ---
> target/arm/helper.c | 34 +++++++++++++++++++++++++++-------
> 1 file changed, 27 insertions(+), 7 deletions(-)
> +static int vae2_tlbmask(CPUARMState *env)
> +{
> + if (arm_hcr_el2_eff(env) & HCR_E2H) {
> + return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2;
> + } else {
> + return ARMMMUIdxBit_E2;
> + }
> +}
The TLBI VAE2 docs say the TLB entry has to be invalidated if:
* The entry would be required to translate the specified VA using
the EL2 or the EL2&0 translation regime.
and this isn't conditional on whether HCR_EL2.E2H is 0 or 1.
So given that we don't flush all TLBs when E2H is changed,
I think we need to always flush all of
ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E2
here.
That would make this the same as alle2_tlbmask, which
seems logically correct, since the difference between
TLBI VAE2 and TLBI_ALLE2 is that the former specifies
a VA+ASID (and the ASID should matter if E2H==1 and
be ignored if E2H==0), not which translation regimes
they affect. e2_tlbmask() is probably a better name than
alle2_tlbmask(), in that case.
thanks
-- PMM
- [PATCH v6 25/41] target/arm: Add the hypervisor virtual counter, (continued)
- [PATCH v6 25/41] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2020/02/01
- [PATCH v6 26/41] target/arm: Update timer access for VHE, Richard Henderson, 2020/02/01
- [PATCH v6 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, Richard Henderson, 2020/02/01
- [PATCH v6 28/41] target/arm: Add VHE system register redirection and aliasing, Richard Henderson, 2020/02/01
- [PATCH v6 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Richard Henderson, 2020/02/01
- [PATCH v6 29/41] target/arm: Add VHE timer register redirection and aliasing, Richard Henderson, 2020/02/01
- [PATCH v6 31/41] target/arm: Flush tlbs for E2&0 translation regime, Richard Henderson, 2020/02/01
- Re: [PATCH v6 31/41] target/arm: Flush tlbs for E2&0 translation regime,
Peter Maydell <=
- [PATCH v6 32/41] target/arm: Update arm_phys_excp_target_el for TGE, Richard Henderson, 2020/02/01
- [PATCH v6 33/41] target/arm: Update {fp,sve}_exception_el for VHE, Richard Henderson, 2020/02/01
- [PATCH v6 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps, Richard Henderson, 2020/02/01
- [PATCH v6 35/41] target/arm: Update get_a64_user_mem_index for VHE, Richard Henderson, 2020/02/01
- [PATCH v6 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE, Richard Henderson, 2020/02/01
- [PATCH v6 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max, Richard Henderson, 2020/02/01
- [PATCH v6 38/41] target/arm: Move arm_excp_unmasked to cpu.c, Richard Henderson, 2020/02/01
- [PATCH v6 40/41] target/arm: Use bool for unmasked in arm_excp_unmasked, Richard Henderson, 2020/02/01
- [PATCH v6 41/41] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt, Richard Henderson, 2020/02/01
- [PATCH v6 39/41] target/arm: Pass more cpu state to arm_excp_unmasked, Richard Henderson, 2020/02/01