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[PATCH v3 20/20] target/arm: Enable ARMv8.2-UAO in -cpu max
From: |
Richard Henderson |
Subject: |
[PATCH v3 20/20] target/arm: Enable ARMv8.2-UAO in -cpu max |
Date: |
Mon, 3 Feb 2020 14:47:16 +0000 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu64.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 57fbc5eade..1359564c55 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -676,6 +676,10 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
cpu->isar.id_aa64mmfr1 = t;
+ t = cpu->isar.id_aa64mmfr2;
+ t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
+ cpu->isar.id_aa64mmfr2 = t;
+
/* Replicate the same data to the 32-bit id registers. */
u = cpu->isar.id_isar5;
u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
--
2.20.1
- [PATCH v3 14/20] target/arm: Set PAN bit as required on exception entry, (continued)
- [PATCH v3 15/20] target/arm: Implement ATS1E1 system registers, Richard Henderson, 2020/02/03
- [PATCH v3 16/20] target/arm: Enable ARMv8.2-ATS1E1 in -cpu max, Richard Henderson, 2020/02/03
- [PATCH v3 17/20] target/arm: Add ID_AA64MMFR2_EL1, Richard Henderson, 2020/02/03
- [PATCH v3 18/20] target/arm: Update MSR access to UAO, Richard Henderson, 2020/02/03
- [PATCH v3 19/20] target/arm: Implement UAO semantics, Richard Henderson, 2020/02/03
- [PATCH v3 20/20] target/arm: Enable ARMv8.2-UAO in -cpu max,
Richard Henderson <=