Re: [PATCH v3 14/20] target/arm: Set PAN bit as required on exception entry

[Richard Henderson]

On 2/8/20 8:45 AM, Richard Henderson wrote:
> On 2/7/20 6:01 PM, Peter Maydell wrote:
>>> +        /* CPSR.PAN is preserved unless target is EL1 and SCTLR.SPAN == 0. 
>>> */
>>> +        if (cpu_isar_feature(aa64_pan, env_archcpu(env))
>>> +            && new_el == 1
>>> +            && !(env->cp15.sctlr_el[1] & SCTLR_SPAN)) {
>>> +            env->uncached_cpsr |= CPSR_PAN;
>>> +        }
>> This doesn't catch the "taking exception to EL3 and AArch32 is EL3"
>> case, which is also supposed to honour SCTLR.SPAN.
>>
>> Given where this code is, we know we're taking an exception to
>> AArch32 and that we're not going to Hyp mode, so in fact every
>> case where we get here is one where we should honour SCTLR.SPAN
>> and I think we can just drop the "new_el == 1" part of the condition.
> 
> Presumably that becomes env->cp15.sctlr_el[new_el] as well, so that we get the
> secure version of the sctlr.

Actually, there's another clause that I missed before:

  # When the target of the exception is EL3, from Non-secure
  # state, this bit is set to 0 regardless
  # of the value of the Secure SCTLR.SPAN bit.

See G8.2.33.  Will fix for v4.


r~