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[PATCH rc5 17/32] target/avr: Initialize TCG register variables
From: |
Aleksandar Markovic |
Subject: |
[PATCH rc5 17/32] target/avr: Initialize TCG register variables |
Date: |
Fri, 7 Feb 2020 02:57:45 +0100 |
From: Michael Rolnik <address@hidden>
Initialize TCG register variables.
Co-developed-by: Richard Henderson <address@hidden>
Co-developed-by: Michael Rolnik <address@hidden>
Signed-off-by: Michael Rolnik <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
---
target/avr/translate.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index a6e6748..becf096 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -129,6 +129,36 @@ struct DisasContext {
};
+void avr_cpu_tcg_init(void)
+{
+ int i;
+
+#define AVR_REG_OFFS(x) offsetof(CPUAVRState, x)
+ cpu_pc = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc");
+ cpu_Cf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf");
+ cpu_Zf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf");
+ cpu_Nf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf");
+ cpu_Vf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf");
+ cpu_Sf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf");
+ cpu_Hf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf");
+ cpu_Tf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf");
+ cpu_If = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If");
+ cpu_rampD = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "rampD");
+ cpu_rampX = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "rampX");
+ cpu_rampY = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "rampY");
+ cpu_rampZ = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "rampZ");
+ cpu_eind = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind");
+ cpu_sp = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp");
+ cpu_skip = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip");
+
+ for (i = 0; i < NUMBER_OF_CPU_REGISTERS; i++) {
+ cpu_r[i] = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]),
+ reg_names[i]);
+ }
+#undef AVR_REG_OFFS
+}
+
+
static int to_regs_16_31_by_one(DisasContext *ctx, int indx)
{
return 16 + (indx % 16);
--
2.7.4
- [PATCH rc5 02/32] target/avr: Introduce basic CPU class object, (continued)
[PATCH rc5 18/32] target/avr: Add support for disassembling via option '-d in_asm', Aleksandar Markovic, 2020/02/06
[PATCH rc5 12/32] target/avr: Add instruction translation - Branch Instructions, Aleksandar Markovic, 2020/02/06
[PATCH rc5 17/32] target/avr: Initialize TCG register variables,
Aleksandar Markovic <=
[PATCH rc5 30/32] .travis.yml: Run the AVR acceptance tests, Aleksandar Markovic, 2020/02/06
[PATCH rc5 27/32] tests/machine-none: Add AVR support, Aleksandar Markovic, 2020/02/06
[PATCH rc5 23/32] hw/avr: Add support for loading ELF/raw binaries, Aleksandar Markovic, 2020/02/06
[PATCH rc5 25/32] hw/avr: Add limited support for some Arduino boards, Aleksandar Markovic, 2020/02/06
[PATCH rc5 22/32] target/avr: Register AVR support with the rest of QEMU, Aleksandar Markovic, 2020/02/06
[PATCH rc5 28/32] tests/boot-serial: Test some Arduino boards (AVR based), Aleksandar Markovic, 2020/02/06
[PATCH rc5 32/32] target/avr: Add section into QEMU documentation, Aleksandar Markovic, 2020/02/06
[PATCH rc5 29/32] tests/acceptance: Test the Arduino MEGA2560 board, Aleksandar Markovic, 2020/02/06
[PATCH rc5 10/32] target/avr: Add instruction translation - Register definitions, Aleksandar Markovic, 2020/02/06
[PATCH rc5 31/32] target/avr: Simplify sections in MAINTAINERS file, Aleksandar Markovic, 2020/02/06