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[PULL 03/48] target/arm: Enable HCR_E2H for VHE
From: |
Peter Maydell |
Subject: |
[PULL 03/48] target/arm: Enable HCR_E2H for VHE |
Date: |
Fri, 7 Feb 2020 14:32:58 +0000 |
From: Richard Henderson <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 7 -------
target/arm/helper.c | 6 +++++-
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2a53f5d09be..0e68704a908 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1424,13 +1424,6 @@ static inline void xpsr_write(CPUARMState *env, uint32_t
val, uint32_t mask)
#define HCR_ATA (1ULL << 56)
#define HCR_DCT (1ULL << 57)
-/*
- * When we actually implement ARMv8.1-VHE we should add HCR_E2H to
- * HCR_MASK and then clear it again if the feature bit is not set in
- * hcr_write().
- */
-#define HCR_MASK ((1ULL << 34) - 1)
-
#define SCR_NS (1U << 0)
#define SCR_IRQ (1U << 1)
#define SCR_FIQ (1U << 2)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 19a57a17da5..f5ce05fdf33 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4721,7 +4721,8 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
ARMCPU *cpu = env_archcpu(env);
- uint64_t valid_mask = HCR_MASK;
+ /* Begin with bits defined in base ARMv8.0. */
+ uint64_t valid_mask = MAKE_64BIT_MASK(0, 34);
if (arm_feature(env, ARM_FEATURE_EL3)) {
valid_mask &= ~HCR_HCD;
@@ -4735,6 +4736,9 @@ static void hcr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
*/
valid_mask &= ~HCR_TSC;
}
+ if (cpu_isar_feature(aa64_vh, cpu)) {
+ valid_mask |= HCR_E2H;
+ }
if (cpu_isar_feature(aa64_lor, cpu)) {
valid_mask |= HCR_TLOR;
}
--
2.20.1
- [PULL 00/48] target-arm queue, Peter Maydell, 2020/02/07
- [PULL 01/48] target/arm/monitor: query-cpu-model-expansion crashed qemu when using machine type none, Peter Maydell, 2020/02/07
- [PULL 03/48] target/arm: Enable HCR_E2H for VHE,
Peter Maydell <=
- [PULL 02/48] target/arm: Define isar_feature_aa64_vh, Peter Maydell, 2020/02/07
- [PULL 04/48] target/arm: Add CONTEXTIDR_EL2, Peter Maydell, 2020/02/07
- [PULL 05/48] target/arm: Add TTBR1_EL2, Peter Maydell, 2020/02/07
- [PULL 06/48] target/arm: Update CNTVCT_EL0 for VHE, Peter Maydell, 2020/02/07
- [PULL 07/48] target/arm: Split out vae1_tlbmask, Peter Maydell, 2020/02/07
- [PULL 08/48] target/arm: Split out alle1_tlbmask, Peter Maydell, 2020/02/07
- [PULL 09/48] target/arm: Simplify tlb_force_broadcast alternatives, Peter Maydell, 2020/02/07
- [PULL 10/48] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_*, Peter Maydell, 2020/02/07
- [PULL 11/48] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2, Peter Maydell, 2020/02/07
- [PULL 12/48] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*, Peter Maydell, 2020/02/07